512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Op e ra t io n s
Co n cu rre n t Au t o Pre ch a rg e
An access command (READ or WRITE) to a second bank while an access command with
auto precharge enabled on a first bank is executing is not allowed by SDRAMs, unless
the SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent
auto precharge. Four cases where concurrent auto precharge occurs are defined below.
READ w it h Au t o Pre ch a rg e
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ
to bank m is registered (Figure 31).
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 32 on page 39).
Fig u re 31: READ Wit h Au t o Pre ch a rg e In t e rru p t e d b y a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
t
Idle
BANK n
t
RP - BANK n
RP - BANK m
Internal
States
Precharge
Page Active
READ with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
DOUT
DOUT
DOUT
DOUT
a
a + 1
d
d + 1
CL = 3 (bank n)
CL = 3 (bank m)
DON’T CARE
Notes: 1. DQM is LOW.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
38
MICRON [ MICRON TECHNOLOGY ]
