512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Ele ct rica l Sp e cifica t io n s
Ta b le 11:
Ele ct rica l Ch a ra ct e rist ics a n d Re co m m e n d e d AC Op e ra t in g Co n d it io n s
Notes: 5, 6, 8, 9, 11; notes appear on pages 51–52
AC Ch a ra ct e rist ics
-75
-8
Pa ra m e t e r
Sym b o l
Min
Ma x
Min
Ma x
Un it s No t e s
CL = 3
CL = 2
tAC (3)
tAC (2)
tAH
tAS
tCH
6
9
7
9
ns
ns
ns
ns
ns
ns
Access time from CLK (pos. edge)
1
1.5
3
1
2.5
3
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
tCL
3
3
CL = 3
CL = 2
tCK (3)
tCK (2)
tCKH
tCKS
tCMH
tCMS
tDH
7.5
9.6
1
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
tCK
ns
ns
ns
23
23
10
1
CKE hold time
2.5
1
2.5
1
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
1.5
1
2.5
1
tDS
1.5
2.5
Data-in setup time
CL = 3
CL = 2
tHZ (3)
tHZ (2)
tLZ
tOH
tRAS
tRC
tRCD
tREF
tRFC
tRP
tRRD
tT
6
9
7
9
10
10
Data-out High-Z time
1
2.5
44
1
Data-out Low-Z time
2.5
48
72
20
Data-out hold time (load)
120,000
64
120,000
64
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE command period
ACTIVE-to-READ or WRITE delay
Refresh period (8,192 rows)
AUTO REFRESH period
67.5
19
80
19
2
80
19
2
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
0.3
15
80
1.2
0.5
15
80
1.2
7
tWR
tXSR
31
20
WRITE recovery time
Exit SELF REFRESH-to-ACTIVE command
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
47
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