512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Tim in g Dia g ra m s
Fig u re 37: Po w e r-Do w n Mo d e
T0
T1
T2
Tn + 1
Tn + 2
( (
) )
t
t
CK
CL
CLK
CKE
( (
) )
t
CH
t
t
CKS
CKS
( (
) )
t
t
CKS CKH
t
t
CMS CMH
( (
) )
COMMAND
DQM
PRECHARGE
NOP
NOP
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
( (
) )
A0–A9, A11, A12
A10
ROW
ROW
( (
) )
ALL BANKS
( (
) )
( (
) )
SINGLE BANK
t
t
AH
AS
( (
) )
BA0, BA1
DQ
BANK
BANK(S)
( (
) )
High-Z
( (
) )
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
Notes: 1. Violating refresh requirements during power-down may result in a loss of data.
See Table 11 on page 47.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
54
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