512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Tim in g Dia g ra m s
Fig u re 48: WRITE – Wit h o u t Au t o Pre ch a rg e
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
t
CMS
CMH
DQM
t
t
t
t
AH
AS
ADDR
ROW
t
ROW
ROW
BANK
COLUMN
m
AS
AH
AH
ALL BANKs
ROW
t
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
AS
BANK
BA0, BA1
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DIN
m
DIN
m
+ 1
DIN
m
+ 2
DIN m
+ 3
DQ
t
t
t
t
RP
t
2
RCD
RAS
RC
WR
DON’T CARE
Notes: 1. For this example, BL = 1, and the WRITE burst is followed by an auto precharge.
2. 15ns is required between <DIN m + 3> and the PRECHARGE command, regardless of fre-
quency.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
65
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