512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Figure 13:
Random READ Accesses
T0
CLK
T1
T2
T3
T4
T5
COMMAND
READ
READ
READ
READ
NOP
NOP
ADDRESS
BANK,
COL
n
BANK,
COL
a
BANK,
COL
x
BANK,
COL
m
DQ
CL = 2
D
OUT
n
D
OUT
a
D
OUT
x
D
OUT
m
T0
CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
READ
READ
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL
n
BANK,
COL
a
BANK,
COL
x
BANK,
COL
m
DQ
CL = 3
D
OUT
n
D
OUT
a
D
OUT
x
D
OUT
m
DON’T CARE
Notes:
1. Each READ command may be to any bank. DQM is LOW.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 14 on page 27 and
to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-
out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or
remain High-Z), regardless of the state of the DQM signal, provided the DQM was active
on the clock just prior to the WRITE command that truncated the READ command. If
not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during
T4 (in Figure 15 on page 28) then the WRITEs at T5 and T7 would be valid, while the
WRITE at T6 would be invalid.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
26
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©2005 Micron Technology, Inc. All rights reserved.
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