512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 48:
CLK
tCKS
CKE
tCMS
COMMAND
tCMH
NOP
WRITE
NOP
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
WRITE – Without Auto Precharge
T0
tCK
tCKH
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
T9
ACTIVE
tCMS tCMH
DQM
tAS
ADDR
tAH
COLUMN
m
ALL BANKs
ROW
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
BANK
ROW
ROW
tAS
A10
tAH
ROW
tAS
BA0, BA1
tAH
BANK
tDS
DQ
tRCD
tRAS
tRC
tDH
tDS
tDH
tDS
tDH
tDS
tDH
D
IN
m
D
IN
m
+ 1
D
IN
m
+ 2
D
IN
m
+ 3
tWR
2
tRP
DON’T CARE
Notes:
1. For this example, BL = 1, and the WRITE burst is followed by an auto precharge.
2. 15ns is required between <D
IN
m
+ 3> and the PRECHARGE command, regardless of fre-
quency.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
65
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
