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MT48LC64M8A2 参数 Datasheet PDF下载

MT48LC64M8A2图片预览
型号: MT48LC64M8A2
PDF下载: 下载PDF文件 查看货源
内容描述: 512MB X4,X8 , X16 SDRAM [512Mb x4, x8, x16 SDRAM]
分类和应用: 动态存储器
文件页数/大小: 68 页 / 2505 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb: x4, x8, x16 SDRAM
Operations
Figure 18:
WRITE Burst
T0
CLK
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL
n
DQ
D
IN
n
D
IN
n
+1
Transitioning Data
Don’t Care
Note:
BL = 2. DQM is LOW.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
After the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 21 on page 30. Data
n
+ 1 is either the
last of a burst of two or the last desired of a longer burst.
Figure 19:
WRITE-to-WRITE
T0
CLK
T1
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL
n
BANK,
COL
b
DQ
D
IN
n
D
IN
n
+1
D
IN
b
Transitioning Data
Don’t Care
Note:
DQM is LOW. Each WRITE command may be to any bank.
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.