128Mb: x4, x8, x16
SDRAM
FUNCTIONAL BLOCK DIAGRAM
8 Meg x 16 SDRAM
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
COMMAND
DECODE
MODE REGISTER
REFRESH 12
COUNTER
12
12
ROW-
ADDRESS
MUX
12
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 512 x 16)
2
2
DQML,
DQMH
SENSE AMPLIFIERS
16
4096
DATA
OUTPUT
REGISTER
2
A0-A11,
BA0, BA1
ADDRESS
REGISTER
BANK
CONTROL
LOGIC
14
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
16
512
(x16)
16
DQ0-
DQ15
2
DATA
INPUT
REGISTER
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
9
9
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
