128Mb: x4, x8, x16
SDRAM
Burst Type
Accesses within a given burst may be programmed to
be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined
by the burst length, the burst type and the starting col-
umn address, as shown in Table 1.
Table 1
Burst Definition
Burst
Length
Starting Column Order of Accesses Within a Burst
Address
Type = Sequential Type = Interleaved
A0
0
1
A1 A0
0
0
0
1
1
0
1
1
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
2
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
4
11
10
9
8
7
6
5
4
3
BT
2
1
0
Mode Register (Mx)
Reserved* WB
Op Mode
CAS Latency
Burst Length
*Should program
M11, M10 = “0, 0”
to ensure compatibility
with future devices.
M2
M1 M0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
8
Full
Page
(y)
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
n = A0-A11/9/8
Cn + 3, Cn + 4...
…Cn - 1,
(location 0-y)
Cn…
M3
0
1
Burst Type
Sequential
Interleaved
M6 M5 M4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M8
0
-
M7
0
-
M6-M0
Defined
-
Operating Mode
Standard Operation
All other states reserved
M9
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
NOTE:
1. For full-page accesses: y = 2,048 (x4), y = 1,024
(x8), y = 512 (x16).
2. For a burst length of two, A1-A9, A11 (x4), A1-A9
(x8) or A1-A8 (x16) select the block-of-two burst;
A0 selects the starting column within the block.
3. For a burst length of four, A2-A9, A11 (x4), A2-A9
(x8) or A2-A8 (x16) select the block-of-four burst;
A0-A1 select the starting column within the block.
4. For a burst length of eight, A3-A9, A11 (x4), A3-
A9 (x8) or A3-A8 (x16) select the block-of-eight
burst; A0-A2 select the starting column within the
block.
5. For a full-page burst, the full row is selected and
A0-A9, A11 (x4), A0-A9 (x8) or A0-A8 (x16) select
the starting column.
6. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
7. For a burst length of one, A0-A9, A11 (x4), A0-A9
(x8) or A0-A8 (x16) select the unique column to be
accessed, and mode register bit M3 is ignored.
Figure 1
Mode Register Definition
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
10
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©2001, Micron Technology, Inc.
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