256Mb: x4, x8, x16 SDRAM
Power-Down
Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN-
HIBIT when no accesses are in progress. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CKE, for maximum power
savings while in standby. The device cannot remain in the power-down state longer
than the refresh period (64ms) because no REFRESH operations are performed in this
mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT with CKE
HIGH at the desired clock edge (meeting
t
CKS).
Figure 54: Power-Down Mode
T0
CLK
T1
T2
tCH
Tn + 1
tCKS
Tn + 2
tCK
tCL
tCKS
CKE
tCKS
tCKH
((
))
((
))
((
))
tCMS tCMH
Command
PRECHARGE
NOP
NOP
((
))
((
))
((
))
((
))
((
))
((
))
NOP
ACTIVE
DQM
Address
All banks
Row
A10
Single bank
((
))
((
))
Row
tAS
BA0, BA1
tAH
Bank(s)
((
))
((
))
((
))
Bank
DQ
High-Z
Two clock cycles
Precharge all
active banks
All banks idle, enter
power-down mode
Input buffers gated off
while in power-down mode
Exit power-down mode
All banks idle
Don’t Care
Note:
1. Violating refresh requirements during power-down may result in a loss of data.
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. S 12/12 EN
83
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
1999 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
