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MT48LC4M32B2 参数 Datasheet PDF下载

MT48LC4M32B2图片预览
型号: MT48LC4M32B2
PDF下载: 下载PDF文件 查看货源
内容描述: 128MB : X32 SDRAM MT48LC4M32B2 â ???? 1梅格×32× 4银行 [128Mb: x32 SDRAM MT48LC4M32B2 – 1 Meg x 32 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 79 页 / 3554 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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128Mb: x32 SDRAM
Commands
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to the selected device
(CS# is LOW). This prevents unwanted commands from being registered during idle or
wait states. Operations already in progress are not affected.
LOAD MODE REGISTER (LMR)
The mode registers are loaded via inputs A[n:0] (where An is the most significant ad-
dress term), BA0, and BA1(see Mode Register (page 37)). The LOAD MODE REGISTER
command can only be issued when all banks are idle and a subsequent executable com-
mand cannot be issued until
t
MRD is met.
ACTIVE
The ACTIVE command is used to activate a row in a particular bank for a subsequent
access. The value on the BA0, BA1 inputs selects the bank, and the address provided se-
lects the row. This row remains active for accesses until a PRECHARGE command is is-
sued to that bank. A PRECHARGE command must be issued before opening a different
row in the same bank.
Figure 8: ACTIVE Command
CLK
CKE
CS#
HIGH
RAS#
CAS#
WE#
Address
Row address
BA0, BA1
Bank address
Don’t Care
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
25
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2001 Micron Technology, Inc. All rights reserved.