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MT48LC4M32B2P-7 参数 Datasheet PDF下载

MT48LC4M32B2P-7图片预览
型号: MT48LC4M32B2P-7
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC4M32B2 â ???? 1梅格×32× 4银行 [SDR SDRAM MT48LC4M32B2 – 1 Meg x 32 x 4 Banks]
分类和应用: 内存集成电路光电二极管动态存储器时钟
文件页数/大小: 80 页 / 4594 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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128Mb: x32 SDRAM
Features
SDR SDRAM
MT48LC4M32B2 – 1 Meg x 32 x 4 Banks
Features
• PC100-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh mode (not available on AT devices)
• Auto refresh
– 64ms, 4096-cycle refresh (15.6µs/row; commer-
cial and industrial)
– 16ms, 4096-cycle refresh (3.9µs/row; automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• Supports CAS latency (CL) of 1, 2, and 3
Table 1: Address Table
Parameter
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
4 Meg x 32
1 Meg x 32 x 4 banks
4K
4K A[11:0]
4 BA[1:0]
256 A[7:0]
Options
• Configuration
– 4 Meg x 32 (1 Meg x 32 x 4 banks)
• Package – OCPL
– 86-pin TSOP II (400 mil)
– 86-pin TSOP II (400 mil) Pb-free
– 90-ball VFBGA (8mm x 13mm)
– 90-ball VFBGA (8mm x 13mm) Pb-
free
• Timing (cycle time)
– 6ns (166 MHz)
– 7ns (143 MHz)
• Revision
• Operating temperature range
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
– Automotive (–40°C to +105°C)
Notes:
1. Off-center parting line.
2. Available on -6 and -7.
3. Contact Micron for availability.
Marking
4M32B2
TG
P
F5
B5
-6
-7
:G, :L
None
IT
AT
Table 3: 128Mb (x32) SDR Part Numbering
Part Numbers
MT48LC4M32B2TG
MT48LC4M32B2P
MT48LC4M32B2F5
MT48LC4M32B2B5
Note:
Architecture
4 Meg x 32
4 Meg x 32
4 Meg x 32
4 Meg x 32
Table 2: Key Timing Parameters
CL = CAS (READ) latency
Speed
Grade
-6
-7
Clock
Frequency
166 MHz
143 MHz
Access
Time
CL = 3
5.5ns
5.5ns
Setup
Time
1.5ns
2ns
Hold
Time
1ns
1ns
1. FBGA Device Decoder:
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. P 9/11 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2001 Micron Technology, Inc. All rights reserved.