256Mb: x4, x8, x16 SDRAM
Functional Block Diagrams
Figure 2: 32 Meg x 8 Functional Block Diagram
CKE
CLK
CS#
WE#
CAS#
RAS#
COMMAND
DECODE
CONTROL
LOGIC
BANK2
BANK3
BANK1
MODE REGISTER
12
REFRESH 13
COUNTER
ROW-
ADDRESS
MUX
13
13
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
BANK0
MEMORY
ARRAY
(8192 x 1024 x 8)
1
1
DQM
SENSE AMPLIFIERS
8
8192
DATA
OUTPUT
REGISTER
2
A[12:0]
BA[1:0]
15
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
1024
(x8)
COLUMN
DECODER
8
DQ[7:0]
8
DATA
INPUT
REGISTER
10
COLUMN-
ADDRESS
COUNTER/
LATCH
10
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
9
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1999 Micron Technology, Inc. All rights reserved.
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