256Mb: x4, x8, x16
SDRAM
SYNCHRONOUS
DRAM
FEATURES
• PC66-, PC100-, and PC133-compliant
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
MT48LC64M4A2 – 16 Meg x 4 x 4 banks
MT48LC32M8A2 – 8 Meg x 8 x 4 banks
MT48LC16M16A2 – 4 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web site:
PIN ASSIGNMENT (Top View)
54-Pin TSOP
x4 x8 x16
-
-
-
-
-
-
-
-
-
-
NC
NC
DQ0
NC NC
DQ0 DQ1
NC NC
NC
DQ2
NC NC
DQ1 DQ3
NC
V
DD
DQ0
V
DD
Q
DQ1
DQ2
VssQ
DQ3
DQ4
V
DD
Q
DQ5
DQ6
VssQ
DQ7
V
DD
DQML
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
x16 x8 x4
-
Vss
DQ15 DQ7
VssQ
-
DQ14
NC
DQ13 DQ6
V
DD
Q
-
DQ12
NC
DQ11 DQ5
VssQ
-
DQ10
NC
DQ9 DQ4
V
DD
Q
-
DQ8
NC
-
Vss
-
NC
DQMH DQM
-
CLK
CKE
-
A12
-
A11
-
A9
-
A8
-
A7
-
A6
-
A5
-
A4
-
Vss
-
-
NC
-
NC
DQ3
-
NC
NC
-
NC
DQ2
-
NC
OPTIONS
• Configurations
64 Meg x 4
(16 Meg x 4 x 4 banks)
32 Meg x 8
( 8 Meg x 8 x 4 banks)
16 Meg x 16 ( 4 Meg x 16 x 4 banks)
• WRITE Recovery (
t
WR)
t
WR = “2 CLK”
1
MARKING
64M4
32M8
16M16
-
NC
-
NC
-
-
DQM
A2
• Package/Pinout
54-pin TSOP II OCPL
2
(400 mil)
60-ball FBGA (8mm x 16mm) (x4, x8)
54-ball FBGA (8mm x 14mm) (x16 only)
• Timing (Cycle Time)
7.5ns @ CL = 2 (PC133)
7.5ns @ CL = 3 (PC133)
• Self Refresh
Standard
Low power
• Operating Temperature
Commercial (0
o
C to +70
o
C)
Industrial (-40
o
C to +85
o
C)
NOTE:
1.
2.
3.
4.
5.
-
-
-
-
-
-
-
-
-
-
-
-
Note:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TG
FB
4, 5
FG
3
The # symbol indicates signal is active LOW. A dash (–)
indicates x8 and x4 pin function is same as x16 pin function.
64 Meg x 4
32 Meg x 8
16 Meg x 16
16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks
8K
8K
8K
8K (A0–A12)
8K (A0–A12)
8K (A0–A12)
4 (BA0, BA1)
2K (A0–A9, A11)
4 (BA0, BA1)
1K (A0–A9)
4 (BA0, BA1)
512 (A0–A8)
-7E
-75
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
None
L
3
KEY TIMING PARAMETERS
SPEED
GRADE
-7E
-75
-7E
-75
CLOCK
ACCESS TIME
FREQUENCY CL = 2* CL = 3*
143 MHz
133 MHz
133 MHz
100 MHz
–
–
5.4ns
6ns
5.4ns
5.4ns
–
–
SETUP
TIME
1.5ns
1.5ns
1.5ns
1.5ns
HOLD
TIME
0.8ns
0.8ns
0.8ns
0.8ns
None
IT
3
Refer to Micron Technical Note TN-48-05.
Off-center parting line.
Consult Micron for availability.
Not available in x16 configuration.
Actual FBGA part marking shown on page 58.
Part Number Example:
*CL = CAS (READ) latency
MT48LC16M16A2TG-75
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
MICRON [ MICRON TECHNOLOGY ]
