ADVANCE
‡
256Mb: x16, x32
2.5V V
EXT
, 1.8V V
DD
, 1.8V V
DD
Q, RLDRAM
REDUCED LATENCY
DRAM (RLDRAM)
FEATURES
• 2.5V V
EXT
, 1.8V V
DD
, 1.8V V
DD
Q I/O
• Cyclic bank addressing for maximum data out
bandwidth
• Non-multiplexed addresses
• Non-interruptible sequential burst of two (2-bit
prefetch) and four (4-bit prefetch) DDR
• Target 600 Mb/s/p data rate
• Programmable Read Latency (RL) of 5-8
• Data valid signal (DVLD) activated as read data is
available
• Data Mask signals (DM0/DM1) to mask first and
second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• Pseudo-HSTL 1.8V I/O Supply
• Internal Auto Precharge
• Refresh requirements: 32ms at 100°C junction
temperature (8K refresh for each bank, 64K refresh
command must be issued in total each 32ms)
MT49H8M32 – 1 Meg x 32 x 8 banks
MT49H16M16 – 2 Meg x 16 x 8 banks
For the latest data sheet, please refer to the Micron
Web site:
www.micron.com/dramds
144-Ball T-FBGA
OPTIONS
• Clock Cycle Timing
3.3ns (300 MHz)
4ns (250 MHz)
5ns (200 MHz)
• Configuration
8 Meg x 32
(1 Meg x 32 x 8 banks)
16 Meg x 16
(2 Meg x 16 x 8 banks)
• Package
144-ball, 11mm x 18.5mm T-FBGA
MARKING
-3.3
-4
-5
MT49H8M32FM
MT49H16M16FM
row/column address multiplexing and is optimized for
fast random access and high-speed bandwidth.
RLDRAM is designed for communication data
storages like transmit or receive buffers in telecommuni-
cation systems as well as data or instruction cache
applications requiring large amounts of memory.
FM
POWER-UP INITIALIZATION
Since the RLDRAM does not have a designated reset
function, the following procedure must be executed in
order to initalize the internal state machine, regulators,
and force the DRAM to be in ready state.
• Apply power, then start clock
• After power on, an initial pause of 200µs is required
• MRS command for 2 clocks and set standard mode
register for 1 clock (2 dummies plus 1 valid MRS set)
• 8 refresh cycles (minimum), one on each bank and
separated by 2,048 cycles (
t
MRSC must be satisfied
between MRS and first REF command)
• Ready for normal operation (
t
RC cycles after the last
refresh command)
VALID PART NUMBERS
PART NUMBER
MT49H8M32FM-xx
MT49H16M16FM-xx
DESCRIPTION
8 Meg x 32
16 Meg x 16
GENERAL DESCRIPTION
The Micron
®
256Mb Reduced Latency DRAM
(RLDRAM) contains 8 banks x32Mb of memory acces-
sible with 32-bit or 16-bit I/Os in a double data rate (DDR)
format where the data is provided and synchronized with
a differential echo clock signal. RLDRAM does not require
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
1
©2002, Micron Technology, Inc.
‡
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
MICRON [ MICRON TECHNOLOGY ]
