16 MEG x 4
EDO DRAM
DRAM
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x4 pinout, timing, functions,
and packages
• 12 row, 12 column addresses (H9) or
13 row, 11 column addresses (G3)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compat-
ible
• Extended Data-Out (EDO) PAGE MODE access
• Optional self refresh (S) for low-power data
retention
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
MT4LC16M4G3, MT4LC16M4H9
PIN ASSIGNMENT (Top View)
32-Pin SOJ
V
CC
DQ0
DQ1
NC
NC
NC
NC
WE#
RAS#
A0
A1
A2
A3
A4
A5
V
CC
32-Pin TSOP
V
CC
DQ0
DQ1
NC
NC
NC
NC
WE#
RAS#
A0
A1
A2
A3
A4
A5
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vss
DQ3
DQ2
NC
NC
NC
CAS#
OE#
NC/A12**
A11
A10
A9
A8
A7
A6
Vss
OPTIONS
• Refresh Addressing
4,096 (4K) rows
8,192 (8K) rows
• Plastic Packages
32-pin SOJ (400 mil)
32-pin TSOP (400 mil)
• Timing
50ns access
60ns access
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
MARKING
H9
G3
DJ
TG
-5
-6
None
S*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vss
DQ3
DQ2
NC
NC
NC
CAS#
OE#
NC/A12**
A11
A10
A9
A8
A7
A6
Vss
**NC on H9 version, A12 on G3 version
16 MEG x 4 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC16M4H9DJ-x
MT4LC16M4H9DJ-x S
MT4LC16M4H9TG-x
MT4LC16M4H9TG-x S
MT4LC16M4G3DJ-x
MT4LC16M4G3DJ-x S
MT4LC16M4G3TG-x
MT4LC16M4G3TG-x S
x = speed
REFRESH
ADDRESSING
4K
4K
4K
4K
8K
8K
8K
8K
PACKAGE
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
REFRESH
Standard
Self
Standard
Self
Standard
Self
Standard
Self
NOTE:
1. The 16 Meg x 4 EDO DRAM base number
differentiates the offerings in one place—
MT4LC16M4H9. The fifth field distinguishes the
address offerings: H9 designates 4K addresses and
G3 designates 8K addresses.
2. The “#” symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
GENERAL DESCRIPTION
The 16 Meg x 4 DRAM is a high-speed CMOS,
dynamic random-access memory device containing
67,108,864 bits and designed to operate from 3V to
3.6V. The MT4LC16M4H9 and MT4LC16M4G3 are
functionally organized as 16,777,216 locations con-
taining 4 bits each. The 16,777,216 memory locations
are arranged in 4,096 rows by 4,096 columns on the H9
version and 8,192 rows by 2,048 columns on the G3
version. During READ or WRITE cycles, each location is
MT4LC16M4H9DJ-6
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
16 Meg x 4 EDO DRAM
D22_2.p65 – Rev. 5/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
