4 MEG x 16
EDO DRAM
DRAM
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x16 pinout, timing, functions,
and package
• 12 row, 10 column addresses (R6)
13 row, 9 column addresses (N3)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data
retention
MT4LC4M16R6, MT4LC4M16N3
For the latest data sheet, please refer to the Micron Web
site:
PIN ASSIGNMENT (Top View)
50-Pin TSOP
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
NC
V
CC
WE#
RAS#
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
V
CC
†
A12
OPTIONS
• Plastic Package
50-pin TSOP (400 mil)
• Timing
50ns access
60ns access
• Refresh Rates
4K
8K
Standard Refresh
Self Refresh
• Operating Temperature Range
Commercial (0°C to +70°C)
MARKING
TG
-5
-6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
NC
V
SS
CASL#
CASH#
OE#
NC
NC
NC/A12
†
A11
A10
A9
A8
A7
A6
V
SS
R6
N3
None
S*
for N3 version, NC for R6 version.
MT4LC4M16R6
Configuration
Refresh
Row Address
Column Addressing
4 Meg x 16
4K
4K (A0-A11)
1K (A0-A9)
MT4LC4M16N3
4 Meg x 16
8K
8K (A0-A12)
512 (A0-A8)
None
NOTE:
1. The “#” symbol indicates signal is active LOW.
*Contact factory for availability.
Part Number Example:
MT4LC4M16R6TG-5
4 MEG x 16 EDO DRAM PART NUMBERS
PART NUMBER
REFRESH
ADDRESSING PACKAGE REFRESH
4K
4K
8K
8K
400-TSOP Standard
400-TSOP
Self
400-TSOP Standard
400-TSOP
Self
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
MT4LC4M16R6TG-x
MT4LC4M16R6TG-x S
MT4LC4M16N3TG-x
MT4LC4M16N3TG-x S
x = speed
4 Meg x 16 EDO DRAM
D29_C.p65 – Rev. 2/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
