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MT4LC8M8E1DJ-6 参数 Datasheet PDF下载

MT4LC8M8E1DJ-6图片预览
型号: MT4LC8M8E1DJ-6
PDF下载: 下载PDF文件 查看货源
内容描述: DRAM [DRAM]
分类和应用: 内存集成电路光电二极管动态存储器
文件页数/大小: 20 页 / 381 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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8 MEG x 8
FPM DRAM
DRAM
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x8 pinout, timing, functions,
and packages
• 13 row, 10 column addresses (E1) or
12 row, 11 column addresses (B6)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-
compatible
• FAST PAGE MODE (FPM) access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data
retention
MT4LC8M8E1, MT4LC8M8B6
PIN ASSIGNMENT (Top View)
32-Pin SOJ
V
CC
DQ0
DQ1
DQ2
DQ3
NC
V
CC
WE#
RAS#
A0
A1
A2
A3
A4
A5
V
CC
32-Pin TSOP
V
CC
DQ0
DQ1
DQ2
DQ3
NC
V
CC
WE#
RAS#
A0
A1
A2
A3
A4
A5
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
DQ7
DQ6
DQ5
DQ4
V
SS
CAS#
OE#
NC/A12**
A11
A10
A9
A8
A7
A6
V
SS
OPTIONS
• Refresh Addressing
4,096 (4K) rows
8,192 (8K) rows
• Plastic Packages
32-pin SOJ (400 mil)
32-pin TSOP (400 mil)
• Timing
50ns access
60ns access
• Refresh Rates
Standard Refresh (64ms period)
Self Refresh (128ms period)
MARKING
B6
E1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
DQ7
DQ6
DQ5
DQ4
Vss
CAS#
OE#
NC/A12**
A11
A10
A9
A8
A7
A6
V
SS
**A12 on E1 version, NC on B6 version
DJ
TG
8 MEG x 8 FPM DRAM PART NUMBERS
PART NUMBER
REFRESH
ADDRESSING
8K
8K
8K
8K
4K
4K
4K
4K
PACKAGE REFRESH
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
Standard
Self
Standard
Self
Standard
Self
Standard
Self
-5
-6
None
S*
NOTE:
1. The 8 Meg x 8 FPM DRAM base number
differentiates the offerings in one place—
MT4LC8M8E1. The fifth field distinguishes
various options: E1 designates an 8K refresh and
B6 designates a 4K refresh for FPM DRAMs.
2. The # symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC8M8E1DJ-x
MT4LC8M8E1DJ-x S
MT4LC8M8E1TG-x
MT4LC8M8E1TG-x S
MT4LC8M8B6DJ-x
MT4LC8M8B6DJ-x S
MT4LC8M8B6TG-x
MT4LC8M8B6TG-x S
x = speed
GENERAL DESCRIPTION
The 8 Meg x 8 DRAMs are high-speed CMOS, dy-
namic random-access memory devices containing
67,108,864 bits organized in a x8 configuration. The
8 Meg x 8 DRAMs are functionally organized as 8,388,608
locations containing eight bits each. The 8,388,608
memory locations are arranged in 8,192 rows by 1,024
columns for the MT4LC8M8E1 or 4,096 rows by 2,048
columns for the MT4LC8M8B6. During READ or WRITE
cycles, each location is uniquely addressed via the
address bits. First, the row address is latched by the
MT4LC8M8E1DJ-5
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
90ns
110ns
50ns
60ns
30ns
35ns
25ns
30ns
13ns
15ns
8 Meg x 8 FPM DRAM
D19_2.p65 – Rev. 5/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.