8 MEG x 8
EDO DRAM
DRAM
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x8 pinout, timing, functions,
and packages
• 12 row, 11 column addresses (C2) or
13 row, 10 column addresses (P4)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-
compatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data
retention
MT4LC8M8P4, MT4LC8M8C2
PIN ASSIGNMENT (Top View)
32-Pin SOJ
V
CC
DQ0
DQ1
DQ2
DQ3
NC
V
CC
WE#
RAS#
A0
A1
A2
A3
A4
A5
V
CC
32-Pin TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
DQ7
DQ6
DQ5
DQ4
V
SS
CAS#
OE#
NC/A12**
A11
A10
A9
A8
A7
A6
V
SS
OPTIONS
• Refresh Addressing
4,096 (4K) rows
8,192 (8K) rows
• Plastic Packages
32-pin SOJ (400 mil)
32-pin TSOP (400 mil)
• Timing
50ns access
60ns access
• Refresh Rates
Standard Refresh (64ms period)
Self Refresh (128ms period)
MARKING
C2
P4
DJ
TG
-5
-6
None
S*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
V
SS
DQ0
DQ7
DQ1
DQ6
DQ2
DQ5
DQ3
DQ4
NC
Vss
V
CC
CAS#
WE#
RAS#
OE#
NC/A12**
A0
A1
A11
A2
A10
A3
A9
A4
A8
A5
A7
V
CC
A6
V
SS
**NC on C2 version and A12 on P4 version
8 MEG x 8 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC8M8C2DJ-x
MT4LC8M8C2DJ-x S
MT4LC8M8C2TG-x
MT4LC8M8C2TG-x S
MT4LC8M8P4DJ-x
MT4LC8M8P4DJ-x S
MT4LC8M8P4TG-x
MT4LC8M8P4TG-x S
x = speed
REFRESH
ADDRESSING
4K
4K
4K
4K
8K
8K
8K
8K
PACKAGE REFRESH
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
Standard
Self
Standard
Self
Standard
Self
Standard
Self
NOTE:
1. The 8 Meg x 8 EDO DRAM base number
differentiates the offerings in one place—
MT4LC8M8C2. The fifth field distinguishes the
address offerings: C2 designates 4K addresses and
P4 designates 8K addresses.
2. The “#” symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
GENERAL DESCRIPTION
The 8 Meg x 8 DRAM is a high-speed CMOS, dy-
namic random-access memory devices containing
67,108,864 bits and designed to operate from 3V to
3.6V. The MT4LC8M8C2 and MT4LC8M8P4 are func-
tionally organized as 8,388,608 locations containing
eight bits each. The 8,388,608 memory locations are
arranged in 4,096 rows by 2,048 columns on the C2
version and 8,192 rows by 1,024 columns on the P4
version. During READ or WRITE cycles, each location is
MT4LC8M8C2DJ-5
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
