PRELIMINARY
MT9M111
SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Figure 1: Functional Block Diagram
SCLK
S
DATA
Sensor Core
1316H x 1048V including black
1/3-inch optical format
Auto black compensation
Programmable analog gain
Programmable exposure
Dual 10-bit ADCs
Low-power preview mode
H/W context switch to/from preview
Bayer RGB output
Pixel Data
SRAM
Line Buffers
CLKIN
STANDBY
OE#
Control Bus
(Two-Wire Serial I/F
Transactions)
Control Bus
(Two-Wire Serial I/F Transactions) +
Sensor control (gains, shutter, etc.)
Image Flow Processor
Camera Control
V
DD
Q/DGNDQ
V
DD
/DGND
V
AA
/AGND
VAAPIX
Control Bus
(Two-Wire
Serial I/F
Trans.)
Image Flow Processor
Colorpipe
Lens shading correction
Color interpolation
Filtered resize and zoom
Defect correction
Color correction
Gamma correction
Color conversion + formatting
Output FIFO
D
OUT
[7:0]
Auto exposure
Auto white balance
Flicker detect/avoid
Camera control:
snapshots, flash, video, clip)
PIXCLK
FRAME_VALID
LINE_VALID
STROBE
Image Data
Figure 2: Internal Registers Grouping
Image Flow Processor
Sensor Core
Registers
R[255:0]
Color Pipeline
Registers
R[255:0]
Camera Control
Registers
R[255:0]
R240 = 0
R240 = 1
R240 = 2
NOTE:
Internal registers are grouped in three address spaces. Program R240 to select the desired address space.
09005aef8136743e pdf/09005aef8136761e zip
MT9M111__SOC1310__2.fm - Rev. C 10/04 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
