Functional Overview
The MT9V135 is a fully-automatic, single-chip camera, requiring only a single power
supply, lens, and clock source for basic operation. Output video is streamed via the
chosen output port. The MT9V135 internal registers are configured using a two-wire
serial interface.
The device can be put into a low-power sleep mode by asserting STANDBY and shutting
down the clock. Output signals can be tri-stated. Both tri-stating output signals and
entry into standby mode can be achieved via two-wire serial interface register writes.
The MT9V135 requires an input clock of 27 MHz to support correct NTSC or PAL timing.
Internal Architecture
Internally, the MT9V135 consists of a sensor core and an image flow processor (IFP). The
IFP is divided in two sections: the colorpipe, and the camera controller. The sensor core
captures raw images that are then input into the IFP. The colorpipe section processes the
incoming stream to create interpolated, color-corrected output, and the camera
controller section controls the sensor core to maintain the desired exposure and color
balance.
The IFP scales the image and an integrated video encoder generates either NTSC or PAL
analog composite output. The MT9V135 supports three different output ports; analog
composite video out, LVDS serial out and CCIR 656 interlaced digital video in parallel 8-
bit format.
Figure 2 shows the major functional blocks of the MT9V135. The built-in NTSC/PAL
encoder and the LVDS Formatter allow simultaneous outputs of composite and digital
video signals. This is especially useful during installation of network cameras and allows
the installer to adjust the camera view and focus using analog monitoring equipment
while the digital viedo is compressed and formatted for IP network delivery.
Figure 2:
Functional Block Diagram
SCLK
SDATA
Sensor Core
.
1/4-inch optical format
.
True interlaced readout
.
Auto black compensation
.
Programmable analog gain
.
Programm able exposure
.
10-bit ADC
Control Bus
+ Sensor control (gains, shutter, etc.)
Pixel Data
.
640H x 480V
SRAM
Line Buffers
LVDSFormatter
and Driver
LVDS_OUT_POS
LVDS_OUT_NEG
EXTCLK
STA ND BY
Control Bus
D
IN
[7:0]
DIN_CLK
NTSC/PAL
Encoder and DAC
Image Flow Processor
Colorpipe
Lens shading correction
Color interpolation
Defect correction
Color correction
Horizontal Interpolator
Gamma correction
Color conversion + formatting
DAC_OUT_POS
DAC_OUT_NEG
Image Flow Processor
Camera Control
V
DD
/DGND
VAA /AGND
VAA PIX
Auto exposure
Auto white balance
Flicker detect/avoid
Control Bus
D
OUT0[7:0]
PIXCLK
FRAME_VALID
LINE_ VALID
Image Data
深圳市圣邦达电子有限公司 电话：086-0755-83723989 传真：086-0755-61351350
�½�站www.sbdsemi.cn
EMAIL：yangbin7575@163.com
联系人：杨 生
13543266942 13642365547
本资料来源来自互联�½�，一切版权�½��½属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正
MICRON [ MICRON TECHNOLOGY ]
