128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AC Read Specifications
Figure 22: Synchronous Burst with Burst Interrupt Read (Non-MUX)
Latency count
t
CH
t
CLK
t
CL
CLK
t
AVCH
t
CHAX
t
AVCH
t
CHAX
A[MAX:0]
t
CHVL
t
VLCH
t
CHVH
t
CHVL
t
VHVL
t
VLCH
t
CHVH
ADV#
t
ELCH
t
ELCH
CE#
OE#
t
GLTV
t
GLTX
t
CHTV
t
CHTX
t
CHTV
WAIT
t
CHQV
t
CHQV
t
CHQX
t
CHQX
DQ[15:0]
Q
Q
Q
RST#
Notes:
1.
2.
3.
4.
5.
WAIT shown as active LOW (RCR[10] = 0) and asserted with data (RCR[8] = 0).
A burst can be interrupted by toggling CE# or ADV#.
For no-wrap bursts, end-of-wordline WAIT states could occur (not shown in this figure).
t
AVQV,
t
ELQV, and
t
VLQV apply to legacy-latching only.
t
ACC and
t
VLVH apply to clock-latching only.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
68
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