128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
General Description
General Description
Micron's 65nm device is the latest generation of StrataFlash
®
wireless memory featur-
ing flexible, multiple-partition, dual-operation architecture. The device provides high-
performance, asynchronous read mode and synchronous-burst read mode using 1.8V
low-voltage, multilevel cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to oc-
cur in one partition while code execution or data reads take place in another partition.
This dual-operation architecture also allows two processors to interleave code opera-
tions while PROGRAM and ERASE operations take place in the background. The multi-
ple partitions allow flexibility for system designers to choose the size of the code and
data segments.
The device is manufactured using 65nm process technologies and is available in indus-
try-standard chip scale packaging.
Functional Overview
This device provides high read and write performance at low voltage on a 16-bit data
bus. The multi-partition architecture provides read-while-write and read-while-erase
capability, with individually erasable memory blocks sized for optimum code and data
storage.
This device is offered in densities from 128Mb to 1Gb. The device supports synchronous
burst reads up to 133 MHz using enhanced CLK latching for all densities on 45nm.
Upon initial power-up or return from reset, the device defaults to asynchronous read
mode. Configuring the read configuration register enables synchronous burst mode
reads. In synchronous burst mode, output data is synchronized with a user-supplied
clock signal. In continuous-burst mode, a data read can traverse partition boundaries. A
WAIT signal simplifies synchronizing the CPU to the memory.
Designed for low-voltage applications, the device supports READ operations with V
CC
at
1.8V, and ERASE and PROGRAM operations with V
PP
at 1.8V or 9.0V. V
CC
and V
PP
can be
tied together for a simple, ultra low-power design. In addition to voltage flexibility, a
dedicated V
PP
connection provides complete data protection when V
PP
is less than
V
PPLK
.
A status register provides status and error conditions of ERASE and PROGRAM opera-
tions.
One-time programmable (OTP) area enables unique identification that can be used to
increase security. Additionally, the individual block lock feature provides zero-latency
block locking and unlocking to protect against unwanted program or erase of the array.
The device offers power-savings features, including automatic power savings mode,
standby mode, and deep power-down mode. For power savings, the device automati-
cally enters APS following a READ cycle. Standby is initiated when the system deselects
the device by de-asserting CE#. Deep power-down provides the lowest power consump-
tion and is enabled by programming in the extended configuration register. DPD is ini-
tiated by asserting the DPD pin.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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2011 Micron Technology, Inc. All rights reserved.
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