256Mb and 512Mb (256Mb/256Mb), P30-65nm
Virtual Chip Enable Description
Virtual Chip Enable Description
The P30-65nm 512Mb devices employ a virtual chip enable feature, which combines
two 256Mb die with a common chip enable, F1-CE# for QUAD+ packages, or CE# for
Easy BGA Packages. The maximum address bit is then used to select between the die
pair with F1-CE#/CE# asserted depending upon the package option used. When chip
enable is asserted and the maximum address bit is LOW (V
IL
), the lower parameter die
is selected; when chip enable is asserted and the maximum address bit is HIGH (V
IH
),
the upper parameter die is selected (see the tables below).
Table 5: Virtual Chip Enable Truth Table for 512Mb (QUAD+ Package)
Die Selected
Lower Param Die
Upper Param Die
F1-CE#
L
L
A24
L
H
Table 6: Virtual Chip Enable Truth Table for 512Mb (Easy BGA Packages)
Die Selected
Lower Param Die
Upper Param Die
CE#
L
L
A25
L
H
Figure 1: 512Mb Easy BGA Block Diagram
Easy BGA 512Mb (Dual Die) Top/Bottom
Parameter Configuration
CE#
WP#
OE#
WE#
CLK
ADV#
Top Parameter Die
256Mb
RST#
VCC
VPP
VCCQ
Bottom Parameter Die
256Mb
VSS
DQ[15:0]
A[MAX:1]
WAIT
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
10
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