256Mb and 512Mb (256Mb/256Mb), P30-65nm
Read Operation
Read Operation
The device supports two read modes: asynchronous page mode and synchronous burst
mode. Asynchronous page mode is the default read mode after device power-up or a re-
set. The Read Configuration Register must be configured to enable synchronous burst
reads of the flash memory array.
The device can be in any of four read states: Read Array, Read Identifier, Read Status or
Read CFI. Upon power-up, or after a reset, the device defaults to Read Array. To change
the read state, the appropriate read command must be written to the device.
Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read
mode and the device is set to Read Array. However, to perform array reads after any oth-
er device operation (e.g. write operation), the Read Array command must be issued in
order to read from the flash memory array.
Asynchronous page-mode reads can only be performed when Read Configuration Reg-
ister bit RCR.15 is set.
To perform an asynchronous page-mode read, an address is driven onto the Address
bus, and CE# and ADV# are asserted. WE# and RST# must already have been deasser-
ted. WAIT is deasserted during asynchronous page mode. ADV# can be driven high to
latch the address, or it must be held low throughout the read cycle. CLK is not used for
asynchronous page-mode reads, and is ignored. If only asynchronous reads are to be
performed, CLK should be tied to a valid VIH or VSS level, WAIT signal can be floated and
ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial access
time tAVQV delay.
In asynchronous page mode, sixteen data words are “sensed” simultaneously from the
flash memory array and loaded into an internal page buffer. The buffer word corre-
sponding to the initial address on the Address bus is driven onto DQ[15:0] after the ini-
tial access delay. The lowest four address bits determine which word of the 16-word
page is output from the data buffer at any given time.
Note: Asynchronous page read mode is only supported in main array.
Synchronous Burst-Mode Read
Read Configuration register bits RCR[15:0] must be set before synchronous burst opera-
tion can be performed. Synchronous burst mode can be performed for both array and
non-array reads such as Read ID, Read Status or Read Query.
To perform a synchronous burst-read, an initial address is driven onto the Address bus,
and CE# and ADV# are asserted. WE# and RST# must already have been deasserted.
ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can re-
main asserted throughout the burst access, in which case the address is latched on the
next valid CLK edge while ADV# is asserted.
During synchronous array and non-array read modes, the first word is output from the
data buffer on the next valid CLK edge after the initial access latency delay. Subsequent
data is output on valid CLK edges following a minimum delay. However, for a synchro-
nous non-array read, the same word of data will be output on successive clock edges
until the burst length requirements are satisfied. Refer to the timing diagrams for more
detailed information.
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
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