256Mb and 512Mb (256Mb/256Mb), P30-65nm
Registers
Figure 15: End of Wordline Timing Diagram
Latency Count
CLK
A[Max:1]
DQ[15:0]
Address
Data
Data
Data
ADV #
OE #
WAIT
EOWL
Table 19: End of Wordline Data and WAIT State Comparison
P30-130nm
P30-65nm
Latency Count
Data States
WAIT States
Not Supported
0 to 1
Data States
WAIT States
1
2
Not Supported
Not Supported
Not Supported
0 to 1
4
16
16
16
16
16
16
16
16
16
16
16
16
16
16
3
4
0 to 2
0 to 2
4
4
0 to 3
0 to 3
5
4
0 to 4
0 to 4
6
4
0 to 5
0 to 5
7
4
0 to 6
0 to 6
8
Not Supported
Not Supported
0 to 7
9
0 to 8
10
11
12
13
14
15
0 to 9
0 to 10
0 to 11
0 to 12
0 to 13
0 to 14
WAIT Signal Polarity and Functionality
The WAIT Polarity bit (WP), RCR.10 determines the asserted level (VOH or VOL) of WAIT.
When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is asserted
low. WAIT changes state on valid clock edges during active bus cycles (CE# asserted,
OE# asserted, RST# deasserted).
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p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
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