Numonyx
®
P33-65nm Flash Memory
128-Mbit, 64-Mbit Single Bit per Cell (SBC)
Datasheet
Product Features
High performance:
— 60ns initial access time for Easy BGA
— 70ns initial access time for TSOP
— 25ns 8-word asynchronous-page read
mode
— 52MHz with zero wait states, 17ns clock-to-
data output synchronous-burst read mode
— 4-, 8-, 16-, and continuous-word options
for burst mode
— 3.0V buffered programming at 1.8MByte/s
(Typ) using 256-word buffer
— Buffered Enhanced Factory Programming at
3.2MByte/s (typ) using 256-word buffer
Architecture:
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or
bottom configuration
— 128-KByte main blocks
— Blank Check to verify an erased block
Voltage and Power:
— V
CC
(core) voltage: 2.3V – 3.6V
— V
CCQ
(I/O) voltage: 2.3V – 3.6V
— Standby current: 35μA(Typ) for 64-Mbit,
50μA(Typ) for 128-Mbit
— Continuous synchronous read current:
23mA (Typ) at 52 MHz
Security:
— One-Time Programmable Registers:
— 64 OTP bits, programmed with unique
information by Numonyx
— 2112 OTP bits, available for customer
programming
—
—
—
—
—
Absolute write protection: V
PP
= V
SS
Power-transition erase/program lockout
Individual zero-latency block locking
Individual block lock-down capability
Password Access feature
Software:
— 20µs (Typ) program suspend
— 20µs (Typ) erase suspend
— Basic Command Set and Extended Function
Interface (EFI) Command Set compatible
— Common Flash Interface capable
Density and Packaging:
— 56-Lead TSOP package (128-Mbit, 64-Mbit)
— 64-Ball Easy BGA package (128-Mbit, 64-
Mbit)
— 16-bit wide data bus
Quality and Reliability:
— JESD47E Compliant
— Operating temperature: –40°C to +85°C
— Minimum 100,000 erase cycles per block
— 65nm process technology
Datasheet
1
Jul 2011
Order Number: 208034-04
MICRON [ MICRON TECHNOLOGY ]
