512Mb, 1Gb, 2Gb: P30-65nm
Signal Descriptions
Signal Descriptions
Table 4: TSOP and Easy BGA Signal Descriptions
Symbol
A[MAX:1]
Type
Input
Name and Function
Address inputs:
Device address inputs.
Note:
Unused active address pins should not be left floating; tie them to V
CCQ
or V
SS
ac-
cording to specific design requirements.
Address valid:
Active LOW input. During synchronous READ operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# LOW, which-
ever occurs first. In asynchronous mode, the address is latched when ADV# goes HIGH or
continuously flows through if ADV# is held LOW.
Note:
Designs not using ADV# must tie it to V
SS
to allow addresses to flow through.
Chip enable:
Active LOW input. CE# LOW selects the associated die. When asserted, inter-
nal control logic, input buffers, decoders, and sense amplifiers are active. When de-asser-
ted, the associated die is deselected, power is reduced to standby levels, data and wait
outputs are placed in High-Z.
Note:
CE# must be driven HIGH when device is not in use.
Clock:
Synchronizes the device with the system bus frequency in synchronous-read mode.
During synchronous READs, addresses are latched on the rising edge of ADV#, or on the
next valid CLK edge with ADV# LOW, whichever occurs first.
Note:
Designs not using CLK for synchronous read mode must tie it to V
CCQ
or V
SS
.
Output enable:
Active LOW input. OE# LOW enables the device’s output data buffers
during READ cycles. OE# HIGH places the data outputs and WAIT in High-Z.
Reset:
Active LOW input. RST# resets internal automation and inhibits WRITE operations.
This provides data protection during power transitions. RST# HIGH enables normal opera-
tion. Exit from reset places the device in asynchronous read array mode.
Write protect:
Active LOW input. WP# LOW enables the lock-down mechanism. Blocks in
lock-down cannot be unlocked with the Unlock command. WP# HIGH overrides the lock-
down function enabling blocks to be erased or programmed using software commands.
Note:
Designs not using WP# for protection could tie it to V
CCQ
or V
SS
without additional
capacitor.
Write enable:
Active LOW input. WE# controls writes to the device. Address and data are
latched on the rising edge of WE# or CE#, whichever occurs first.
ADV#
Input
CE#
Input
CLK
Input
OE#
RST#
Input
Input
WP#
Input
WE#
V
PP
Input
Power/Input
Erase and program power:
A valid voltage on this pin allows erasing or programming.
Memory contents cannot be altered when V
PP
≤
V
PPLK
. Block erase and program at invalid
V
PP
voltages should not be attempted.
Set V
PP
= V
PPL
for in-system PROGRAM and ERASE operations. To accommodate resistor or
diode drops from the system supply, the V
IH
level of V
PP
can be as low as V
PPL,min
. V
PP
must
remain above V
PPL,min
to perform in-system modification. V
PP
may be 0V during READ op-
erations.
V
PP
can be connected to 9V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9V may reduce block cycling capability.
DQ[15:0]
Input/Output
Data input/output:
Inputs data and commands during WRITE cycles; outputs data during
memory, status register, protection register, and read configuration register reads. Data
balls float when the CE# or OE# are de-asserted. Data is internally latched during writes.
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
15
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