512Mb, 1Gb, 2Gb: P30-65nm
AC Write Specifications
AC Write Specifications
Table 40: AC Write Specifications
Parameter
RST# HIGH recovery to WE# LOW
CE# setup to WE# LOW
WE# write pulse width LOW
Data setup to WE# HIGH
Address setup to WE# HIGH
CE# hold from WE# HIGH
Data hold from WE# HIGH
Address hold from WE# HIGH
WE# pulse width HIGH
V
PP
setup to WE# HIGH
V
PP
hold from status read
WP# hold from status read
WP# setup to WE# HIGH
WE# HIGH to OE# LOW
WE# HIGH to read valid
Write to Asynchronous Read Specifications
WE# HIGH to address valid
Write to Synchronous Read Specifications
WE# HIGH to clock valid
WE# HIGH to ADV# HIGH
WE# HIGH to ADV# LOW
Write Specification with Clock Active
ADV# HIGH to WE# LOW
Clock HIGH to WE# LOW
Notes:
t
VHWL
t
CHWL
t
WHCH/L
t
WHVH
t
WHVL
t
WHAV
Symbol
t
PHWL
t
ELWL
t
WLWH
t
DVWH
t
AVWH
t
WHEH
t
WHDX
t
WHAX
t
WHWL
t
VPWH
t
QVVL
t
QVBL
t
BHWH
t
WHGL
t
WHQV
Min
150
0
50
50
50
0
0
0
20
200
0
0
200
0
t
AVQV
+ 35
0
19
19
7
-
-
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1, 2, 3
1, 2, 3
1, 2, 4
1, 2, 12
1, 2
1, 2, 5
1, 2, 3, 7
1, 2, 3, 7
1, 2, 9
1, 2, 3, 6, 10
1, 2, 3, 6, 8
1, 2, 3, 6, 10
1, 2, 3, 11
1. Write timing characteristics during erase suspend are the same as WRITE-only opera-
tions.
2. A WRITE operation can be terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width LOW (
t
WLWH or
t
ELEH) is defined from CE# or WE# LOW (whichever
occurs last) to CE# or WE# HIGH (whichever occurs first). Thus,
t
WLWH =
t
ELEH =
t
WLEH
=
t
ELWH.
5. Write pulse width HIGH
t
WHWL or
t
EHEL) is defined from CE# or WE# HIGH whichever
occurs first) to CE# or WE# LOW whichever occurs last). Thus,
t
WHWL =
t
EHEL = t
WHEL
=
t
EHWL).
6.
t
WHVH or
t
WHCH/L must be met when transitioning from a WRITE cycle to a synchro-
nous BURST read.
7. V
PP
and WP# should be at a valid level until erase or program success is determined.
8. This specification is only applicable when transitioning from a WRITE cycle to an asyn-
chronous read. See spec
t
WHCH/L and
t
WHVH for synchronous read.
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
85
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2013 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
