BSP 3505D
Contents
Page
4
4
4
5
5
6
6
6
8
9
9
9
9
9
10
11
12
12
13
13
14
14
15
15
16
17
17
17
17
18
18
18
19
19
19
20
20
20
20
Section
1.1.
1.2.
1.3.
2.1.
2.1.1.
2.2.
2.3.
2.4.
3.1.
3.2.
3.2.1.
3.2.2.
3.2.3.
3.2.4.
3.3.
4.1.
4.2.
4.3.
4.4.
4.4.1.
4.4.2.
4.4.3.
4.4.4.
4.4.5.
4.4.6.
4.4.7.
4.4.8.
4.4.9.
4.4.10.
4.4.11.
4.4.12.
4.4.13.
4.4.14.
4.5.
4.5.1.
4.5.2.
4.5.3.
4.5.4.
4.5.5.
Title
BSP 3505D Integrated Functions
Features of the DSP-Section
Features of the Analog Section
Analog Section and SCART Switching Facilities
Standby Mode
BSP 3505DAudio Baseband Processing
Clock and Crystal Specifications
Digital Control Output Pins
Protocol Description
Proposal for BSP 3505D I
2
C Telegrams
Symbols
Write Telegrams
Read Telegrams
Examples
Start Up Sequence: Power Up and I
2
C-Controlling
Register ‘MODE_REG’
DSP Write Registers: Table and Addresses
DSP Read Registers: Table and Addresses
DSP Write Registers: Functions and Values
Volume Loudspeaker Channel
Balance Loudspeaker Channel
Bass Loudspeaker Channel
Treble Loudspeaker Channel
Loudness Loudspeaker Channel
Spatial Effects Loudspeaker Channel
Volume SCART1
Channel Source Modes
Channel Matrix Modes
SCART Prescale
Definition of Digital Control Output Pins
Definition of SCART-Switching Facilities
Beeper
Automatic Volume Correction (AVC)
DSP Read Registers: Functions and Values
Quasi-Peak Detector
BSP Hardware Version Code
BSP Major Revision Code
BSP Product Code
BSP ROM Version Code
PRELIMINARY DATA SHEET
2
Micronas
MICRONAS [ MICRONAS ]
