MAS 3506D
PRELIMINARY DATA SHEET
3.4. Control Registers
Note! Registers not given in the tables must not be
written.
The registers displayed in the following table can be
read and written via I2C commands described (see
Section 3.3.6. and Section 3.3.8.).
Table 3–10: Control Registers
Address
(hex)
R/W Function
Default Name
(hex)
8e
W
DC/DC-Converter Frequency and Voltage
08000
DCCF
The I2C protocol is working only if the processor is active
(WSEN = 1). However, the setting for the DCCF register will
remain active if the WSEN line is deasserted.
DC/DC-Converter Frequency
The frequency is controlled with bits 13...10 and 8.
Setting
bit [13:10]
Frequency/kHz
bit [8] = 0
Frequency/kHz
bit [8] = 1
11 11
11 10
11 01
11 00
10 11
10 10
10 01
10 00
01 11
01 10
01 01
01 00
00 11
00 10
00 01
00 00
156
160
163
167
171
175
179
184
188
194
199
204
210
216
223
230
128
245
253
263
272
283
295
307
320
335
351
368
387
409
433
460
The divider for the CLKI input is determined by the content of the
DCCF register. This register allows 32 settings of the DC/DC con-
verter clock frequency fdc:
fCKLI
-------------------------
=
fSW
2 (m + n)
n
{0, 15}, m {16, 32}
(EQ 1)
In order to reduce interference noise in AM-reception, the oscillator
frequency may be adjusted in 16 steps in order to allow the system
controller to select a base frequency that does not interfere with an
other application. The following algorithm may be used to select an
appropriate value for DCCF:
20
Micronas
MICRONAS [ MICRONAS ]
