MSP 3410 B
9. S-Bus Interface
Digital audio information provided by the DMA2381 via
the AMU is serially transmitted to the MSP 3410 B via the
S-Bus. The MSP 3410 B always has the master function.
The S-Bus interface consists of four pins:
1. S_DA_IN:
Four channels (4*16 bits) per sampling cycle (32 kHz)
are transmitted.
2. S_CL:
Gives the timing for the transmission of S-DATA
(4.608 MHz).
3. S_ID:
After 64 S-CLOCK cycles the S_ID determines the end
of one sampling period.
4. S_DA_OUT:
FM-Demodulator or NICAM decoder output for test pur-
pose.
10. I
2
S Bus Interface
PRELIMINARY DATA SHEET
By means of this standardized interface, additional fea-
ture processors can be connected to the MSP 3410 B.
Two possible formats are supported: The standard
mode (MODE_REG[4]=0) selects the SONY format,
where the I
2
S_WS signal changes at the word bound-
aries. The so-called PHILIPS format, which is character-
ized by a change of the I
2
S_WS signal one I
2
S_CL peri-
od before the word boundaries, is selected by setting
MODE_REG[4]=1.
The MSP 3410 B normally serves as the master on the
I
2
S interface. Here the clock and word strobe lines are
driven by the MSP 3410 B. By setting MODE_REG[3]=1,
the MSP 3410 B is switched to a slave mode. Now these
lines are input to the MSP 3410 B and the master clock
is synchronized to 576 times the I
2
S_WS rate (32 kHz).
No NICAM or D2MAC operation is possible in this mode.
The I
2
S bus interface consists of four pins:
1. I
2
S_DA_IN:
For input, two channels (2*16 bits) per sampling cycle
(32 kHz) are transmitted.
2. I
2
S_DA_OUT:
For output, two channels (2*16 bits) per sampling cycle
(32 kHz) are transmitted.
3. I
2
S_CL:
Gives the timing for the transmission of I
2
S serial data
(1.024 MHz).
4. I
2
S_WS:
The I
2
S_WS word strobe line defines the left and right
sample.
16
ITT Semiconductors
MICRONAS [ MICRONAS ]
