ADVANCE INFORMATION
1. Introduction
The VPC 323xD/324xD is a high-quality, single-chip
video front-end, which is targeted for 4:3 and 16:9, 50/
60 and 100/120 Hz TV sets. It can be combined with
other members of the DIGIT3000 IC family (such as
DDP 33x0A/B, TPU 3040) and/or it can be used with
3rd-party products.
The main features of the VPC 323xD/324xD are
– high-performance adaptive 4H comb filter Y/C sepa-
rator with adjustable vertical peaking
– multi-standard color decoder PAL/NTSC/SECAM
including all substandards
– four CVBS, one S-VHS input, one CVBS output
– two RGB/YC
r
C
b
component inputs, one Fast Blank
(FB) input
– integrated high-quality A/D converters and associ-
ated clamp and AGC circuits
– multi-standard sync processing
– linear horizontal scaling (0.25 ... 4), as well as
non-linear horizontal scaling ‘panorama vision’
– PAL+ preprocessing (VPC 323xD)
– line-locked clock, data and sync, or 656-output inter-
face (VPC 323xD)
– display and deflection control (VPC 324xD)
– peaking, contrast, brightness, color saturation and
tint for RGB/ YC
r
C
b
and CVBS/S-VHS
– high-quality soft mixer controlled by Fast Blank
1 1
--
-
– PIP processing for four picture sizes (
1
,
---
,
------
, or
4 9 16
normal size) with 8 bit resolution
1
---
of
36
– 15 predefined PIP display configurations and expert
mode (fully programmable)
– control interface for external field memory
– I
2
C-Bus Interface
– one 20.25 MHz crystal, few external components
– 80-pin PQFP package
1.1. System Architecture
Fig.1–1 shows the block diagram of the video proces-
sor
CIN
VIN1
VIN2
VIN3
VIN4
VOUT
Analog
Front-end
Adaptive
Comb
Filter
NTSC
PAL
Color
Decoder
NTSC
PAL
SECAM
Saturation
Tint
Y
Mixer
Y
2D Scaler
PIP
Panorama
Mode
Contrast
Brightness
Output
Formatter
ITU-R 656
ITU-R 601
Memory
Control
Y OUT
CrCb
OUT
YCOE
FIFO
CNTL
Cr
Cr
AGC
2×ADC
Cb
Cb
Peaking
RGB/
YCrCb
FB
RGB/
YCrCb
Processing
Y
Analog
Component
U/B
Cr
Matrix
Front-End
Contrast
V/R
Saturation
Cb
Brightness
4 x ADC
FB
FB
Tint
Y/G
I
2
C Bus
Clock
Gen.
Sync
+
Clock
Generation
LL Clock
H Sync
V Sync
AVO
20.25 MHz I
2
C Bus
Fig. 1–1:
.Block diagram of the VPC 323xD
Micronas
5
MICRONAS [ MICRONAS ]
