VSP 94x2A
DATA SHEET
2
3. I C Bus Interface
The transmitted data is internally stored in registers.
The registers are located in four different clock
domains. The Table 3–5 on page 35 shows the four
different clock domains of the VSP 94x2A. The clock
domains are called CP - CVBS processing block
(20.25 MHz domain, clkf20), FP - Front end processing
block (40.5 MHz domain, clkf40), BP - Back end pro-
cessing block (36.0 MHz domain, clkb36) and PP -
PLL processing block (36.0 MHz domain, clkf36).
2
3.1. I C Bus Slave Address
When pin 19 (adr/tdi) is connected to Vss, the
VSP 94x2A reacts on the first I C address (B0h for
write access and B1h for read access). The second
address (B2h and B3h) is active, when pin 19 is con-
nected to Vdd.
2
2
The registers themselves are grouped in an I C bus
2
Table 3–1: I C bus slave addresses B0h and B1h
interface block, one in each domain. The transmitted
2
2
data is received by the I C bus kernel. The I C bus ker-
nel itself is located in the CP domain. This means that
the working frequency is 20.25 MHz. The data is trans-
Write Address1: B0h
Read Address1: B1h
2
mitted to the I C bus interface blocks via an internal
1 0 1 1 0 0 0 0
1 0 1 1 0 0 0 1
serial bus.
For the write process, the I2C bus master has to write
a ‘don’t care’ byte to the subaddress FFh (store com-
mand). This makes the register values available to the
four I2C bus interface blocks (except for the not-take-
over registers, which are used immediately).
2
Table 3–2: I C bus slave addresses B2h and B3h
Write Address2: B2h
Read Address2: B3h
1 0 1 1 0 0 1 0
1 0 1 1 0 0 1 1
In order to have a defined time step for the several
blocks in the different domains, the data are made
valid with internal V-syncs, depending on the different
clock domains.
2
3.1.1. I C Bus Format
2
The subaddresses, where the data are made valid with
the V-sync signal of the 20.25 MHz domain are indi-
cated in the overview of the subaddresses with “V20“.
The others are called “V40”, “V36F” and “V36B”
accordingly.
The VSP 94x2A I C bus interface acts as a slave
receiver and a slave transmitter and provides two dif-
ferent access modes (write, read). All modes run with
a subaddress auto increment. The interface supports
the normal 100 kHz transmission speed as well as the
high speed 400 kHz transmission.
Table 3–3: Write
S
1
0
1
1
0
0
x
0
A
Subaddress
A
Data Byte
A
*****
A
P
S: Start condition
SR: Repeated Start condition
A: Acknowledge
P: Stop condition
NA: Not Acknowledge
Table 3–4: Read
NA
S
1
0
1
1
0
0
x
0
A
A
SR
1
0
1
1
0
0
x
1
A
A
P
34
Aug. 16, 2004; 6251-552-1DS
Micronas
MICRONAS [ MICRONAS ]
