PRODUCT DATABOOK 1996/1997
SG1842/SG1843 Series
C
URRENT
-M
ODE
PWM C
ONTROLLER
P
R O D U C T I O N
D
A T A
S
H E E T
T Y P I C A L A P P L I C AT I O N C I R C U I T S
(continued)
V
CC
V
IN
SG1842/43
5V
8(14)
5V
S
R
R
T
2.5V
V
REF
GOOD LOGIC
R
SLOPE
From V
O
4(7)
OSCILLATOR
C
T
2R
R
i
R
d
2(3)
C
F
R
F
1(1)
5(9)
ERROR
AMP
R
1V
PWM
LATCH
C.S.
COMP
5V
REF
INTERNAL
BIAS
7(12)
V
O
UVLO
2N222A
7(11)
Q1
6(10)
5(8)
R
3(5)
C
R
S
FIGURE 23.
— SLOPE COMPENSATION
Due to inherent instability of current mode converters running above 50% duty cycle, a slope compensation should be added to
either current sense pin or the error amplifier. Figure 23 shows a typical slope compensation technique.
V
REF
R
T
2N2222
4.7K
100K
1K
ERROR AMP
ADJUST
4.7K
5K
I
SENSE
ADJUST
1
SG1842/43
COMP
V
REF
8
A
V
CC
2
V
FB
V
CC
7
0.1µF
0.1µF
1K
OUTPUT
3
I
SENSE
OUTPUT
6
4
R
T
C
T
GROUND
5
C
T
GROUND
FIGURE 24.
— OPEN LOOP LABORATORY FIXTURE
High-peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be
connected to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply
an adjustable ramp to pin 3.
Copyright © 2000
Rev. 1.6a
10/04
13
MICROSEMI [ MICROSEMI CORPORATION ]
