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U405_TO-71 参数 Datasheet PDF下载

U405_TO-71图片预览
型号: U405_TO-71
PDF下载: 下载PDF文件 查看货源
内容描述: 低噪声,低漂移,单片双N沟道JFET [Low Noise, Low Drift, Monolithic Dual N-Channel JFET]
分类和应用:
文件页数/大小: 1 页 / 281 K
品牌: MICROSS [ MICROSS COMPONENTS ]
   
LSU405
LOW NOISE, LOW DRIFT
MONOLITHIC DUAL
N-CHANNEL JFET
Linear Systems replaces discontinued Siliconix U405 with LSU405
The U405/ LSU405 is a Low Noise, Low Drift, Monolithic Dual N-Channel JFET
The LSU405 is a high-performance monolithic dual
JFET featuring extremely low noise, tight offset voltage
and low drift over temperature specifications, and is
targeted for use in a wide range of precision
instrumentation applications. The LSU405 features a 5-
mV offset and 10-µV/°C drift. The LSU405 is a direct
replacement for discontinued Siliconix U405.
The hermetically sealed TO-71 & TO-78 packages are
well suited for military applications. .
(See Packaging Information).
FEATURES 
LOW DRIFT 
LOW NOISE 
LOW PINCHOFF 
ABSOLUTE MAXIMUM RATINGS  
@ 25°C (unless otherwise noted) 
| V 
GS1‐2 
/ T| = 10µV/°C TYP. 
e
n
 = 6nV/Hz @ 10Hz TYP. 
V
p
 = 2.5V TYP. 
U405 / LSU405 Applications:
Wideband Differential Amps
High-Speed,Temp-Compensated Single-
Ended Input Amps
High-Speed Comparators
Impedance Converters and vibrations
detectors.
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL 
BV
GSS
 
BV
GGO
 
 
Y
fSS
 
Y
fS
 
|Y
FS1‐2 
/ Y
 FS
 
DRAIN CURRENT 
 
I
DSS
 
Full Conduction 
0.5 
|I
DSS1‐2 
/ I
DSS
Mismatch at Full Conduction 
‐‐ 
 
 
GATE VOLTAGE 
V
GS
(off) or V
p
 
Pinchoff voltage 
‐0.5 
V
GS
(on) 
Operating Range 
‐‐ 
 
 
GATE CURRENT 
‐I
G
max. 
Operating 
‐‐ 
‐I
G
max. 
High Temperature 
‐‐ 
‐I
GSS
max. 
At Full Conduction 
‐‐ 
‐I
GSS
max. 
High Temperature 
 
OUTPUT CONDUCTANCE 
 
Y
OSS
 
Full Conduction 
‐‐ 
Y
OS
 
Operating 
‐‐ 
 
COMMON MODE REJECTION 
 
CMR 
‐20 log | V 
GS1‐2
/ V 
DS
95 
 
NOISE 
 
NF 
Figure 
‐‐ 
e
n
 
Voltage 
‐‐ 
 
CAPACITANCE 
 
C
ISS
 
Input 
‐‐ 
C
RSS
 
Reverse Transfer 
‐‐ 
Maximum Temperatures 
Storage Temperature 
‐65°C to +150°C 
Operating Junction Temperature 
+150°C 
Maximum Voltage and Current for Each Transistor – Note 1 
‐V
GSS
 
Gate Voltage to Drain or Source 
50V 
‐V
DSO
 
Drain to Source Voltage 
50V 
‐I
G(f)
 
Gate Forward Current 
10mA 
Maximum Power Dissipation 
Device Dissipation @ Free Air – Total                 300mW 
 
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL 
CHARACTERISTICS  VALUE  UNITS  CONDITIONS 
| V 
GS1‐2 
/ T| max. 
DRIFT VS. 
40 
µV/°C  V
DG
=10V, I
D
=200µA 
TEMPERATURE 
T
A
=‐55°C to +125°C 
| V 
GS1‐2 
| max. 
OFFSET VOLTAGE 
20 
mV 
V
DG
=10V, I
D
=200µA 
 
‐‐ 
 
‐‐ 
‐‐ 
 
‐4 
‐‐ 
‐‐ 
 
‐‐ 
0.2 
 
‐‐ 
 
‐‐ 
20 
 
‐‐ 
‐‐ 
 
10 
 
‐2.5 
‐2.3 
 
‐15 
‐10 
100 
 
20 
 
‐‐ 
 
0.5 
‐‐ 
 
1.5 
 
mA 
 
 
pA 
nA 
pA 
pA 
 
µmho 
µmho 
 
dB 
 
dB 
nV/√Hz 
 
pF 
pF 
S
= 0 
 
V
DG
= 10V              V
GS
= 0V 
 
 
V
DS
= 15V               I
D
= 1nA 
              V
DS
=15V                 I
D
=200µA 
 
V
DG
= 15V I
D
= 200µA 
T
A
= +125°C
 
V
DS
=0 
V
DG
= 15V         T
A
= +125°C 
 
V
DG
= 10V              V
GS
= 0V 
V
DG
=  15V            I
D
= 500µA 
 
V
DS 
= 10 to 20V        I
D
=30µA 
V
DS
= 15V      V
GS
= 0V       R
G
= 10M 
f= 100Hz           NBW= 6Hz 
V
DS
=15V   I
D
=200µA   f=10Hz  NBW=1Hz 
 
V
DS
= 15V      I
D
= 200µA      f= 1MHz 
 
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
TO-71 / TO-78 (Top View)
Micross Components Europe
Available Packages:
U405 / LSU405 in TO-71 & TO-78
U405 / LSU405 available as bare die
Please contact
Micross
for full package and die dimensions
Tel: +44 1603 788967
Email:
chipcomponents@micross.com
Web:
http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.