ML1001
v
Pin Description
Symbol
LOAD
DIN
DCLK
BEN
OEN
V
DD
SEN1
CEN1A
SEN2
CEN1B
GND
OOUT
FIN
LCLK
2 kHz
1 kHz
512 Hz
256 Hz
128 Hz
4 Hz
2 Hz
1 Hz
BCLK
DOUT
GND
V
DD
COM1B
S40 to S1
COM1A
V
DD
GND
Pad
1,28
2
3,26
4,25
5
6
7
8
9
10
11
12
13
14,24
15
16
17
18
19
20
21
22
23
27
29
30
31
32 to 71
72
73
74
Description
Load data from the shift register to data register; note 1
Display data input pin
Input pin for the clock of the display data; note 1
Enable pin of the blink function; note 1, note 2
Enable pin of the internal oscillator; note 2
Supply voltage
Enable pin of the segment from S1 to S16; note 1
Enable pin of the COM1A; note 2
Enable pin of the segment from S17 to S40; note 1
Enable pin of the COM1B; note 2
Logic ground
Output pin of the internal oscillator
Input pin of the external/internal clock
Input pin to the LCD display clock; note 1
Output 1/16 frequency of the input to the FIN; note 3
Output 1/32 frequency of the input to the FIN; note 3
Output 1/64 frequency of the input to the FIN; note 3
Output 1/128 frequency of the input to the FIN; note 3
Output 1/256 frequency of the input to the FIN; note 3
Output 1/8192 frequency of the input to the FIN; note 3
Output 1/16384 frequency of the input to the FIN; note 3
Output 1/32768 frequency of the input to the FIN; note 3
Input pin for the blink clock
Output pin for 40-bit Shift register, it shall connect to DIN of next ML1001
Logic ground
Supply voltage
Common driving signal to LCD panel
LCD segment outputs
Common driving signal to LCD panel
Supply voltage
Logic ground
Note :
1. In cascade format of ML1001(ie. ML1001-2U and –3U), one pin is the input of current ML1001 and
the other is for the connection with the corresponding input pin of next ML1001.
2. All Enable pins are active low.
3. Condition : FIN = 32 KHz Clock.
8/13
MINILOGIC [ MINILOGIC DEVICE CORPORATION LIMITED ]
