ML61
Functional Description (Refers to CMOS Output)
1. Firstly, when a voltage, higher than the
4. When the Input Voltage (V
IN
) rises, output
Release Voltage (V
DR
) , is applied to the
become stable once the voltage has
exceeded V
MIN
. The Output Voltage (V
OUT
)
Voltage Input pin (V
IN
), that voltage will
gradually fall. When a voltage higher than
will remain equal to the Ground Voltage
the Detect Voltage (V
DF
) is applied to the
(V
SS
) level until the Input Voltage (V
IN
)
Input Voltage pin (V
IN
), output at V
OUT
reaches the Detect Release Voltage (V
DR
)
will be equal to the input at the V
IN
pin.
level.
High impedance exists on the Output pin 5. When the Input Voltage (V
IN
) rises above
(V
OUT
) with the N-channel open drain
the Detect Release Voltage (V
DR
) level,
configuration. If the pin is pulled-up. V
OUT
output at the Output pin (V
OUT
) is equal to
will be identical to the pull-up voltage.
V
IN
. (High impedance exists with the
2. When the input Voltage (V
IN
) falls below
N-channel open drain output
the Detect Voltage (V
DF
) level, the Output
configuration and V
OUT
follows the
Voltage (V
OUT
) is equal to the Ground
pull-up voltage.)
Voltage (V
SS
) level (detect state). Also
Notes :
applicable to N-channel open drain
1. The difference between V
DR
and V
DF
represents the Hysteresis Range.
configuration.
3. When the Input Voltage (V
IN
) falls below 2. The Propagation Delay Time (t
DLY
)
the Minimum Operating Voltage (V
MIN
)
represents the time it takes for the Input
level, output becomes unstable. In the case
Voltage (V
IN
) to appear at the Output pin
of N-channel open drain configuration, as
(V
OUT
), once the said voltage has exceeded
the output pin is generally pulled-up, the
the Release Voltage (V
DR
) level.
output will be equal to the pull-up
voltage.
Timing Diagram
P6/14
MINILOGIC [ MINILOGIC DEVICE CORPORATION LIMITED ]
