MH89625C
Preliminary Information
TIP
RING
IC
IC
IC
RF1
RF2
IC
VEE
SHK
LED
CSTi
DSTi
C2i
DSTo
F1i
CA
RGND
RD2
RD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
IC
IC
IC
VBAT
LGND
GS
VAC
IC
LCA
VDD
AGND
IC
IC
IC
IC
IC
VREF
VRLY
RD4
RD3
Figure 2 - Pin Connections
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
Name
TIP
RING
IC
IC
IC
RF1
RF2
IC
V
EE
SHK
LED
CSTi
Description
Tip Lead.
Connects to the “Tip” lead of the telephone line.
Ring Lead.
Connects to the “Ring” lead of the telephone line.
Internal Connection:
This pin is internally connected.
Internal Connection:
This pin is internally connected.
Internal Connection:
This pin is internally connected.
Ring Feed 1:
For OPS operation, connects to the external battery backed ringing
generator, see Figure 2.
Ring Feed 2:
For OPS operation, connects to RING through a normally closed relay
contact (K1), see Figure 2.
Internal Connection.
This pin is internally connected.
Negative Supply Voltage:
(-5V)
Switch Hook Detect (Output):
A logic low indicates an off-hook condition.
LED Drive (Output):
Drives an LED directly through an internal 2.2kΩ resistor. A logic
low indicates an off-hook condition.
Control ST-BUS in (Input):
A TTL compatible digital input used to control the function
of the filter/codec. Three modes of operation may be affected by applying to this input
logic high, logic low or an 8-bit serial word, depending on the logic states of CA and F1i.
Functions controlled are: power down, filter gain adjust, loopback, chip testing, and the
SD outputs which control the relay drivers, ring trip circuitry and impedance selection.
Data ST-BUS in (Input):
A TTL compatible digital input which accepts the 8-bit PCM
word from the incoming PCM bus.
Clock Input (Input):
A TTL compatible digital input which accepts the 2048 kHz clock.
Data ST-BUS Out (Output).
A three stage TTL compatible digital output which drives
the 8-bit PCM word to the outgoing PCM bus.
Synchronization Input (Input):
A TTL compatible active low digital input enabling (in
conjunction with CA) the PCM input, PCM output and digital control input. It is internally
sampled on every positive edge of the clock, C2i, and provides frame and channel
synchronization.
13
14
15
16
DSTi
C2i
DSTo
F1i
2-270
MITEL [ MITEL NETWORKS CORPORATION ]
