®
ST-BUS™ FAMILY
MH89760B
T1/ESF Framer & Interface
Preliminary Information
Features
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Complete interface to a bidirectional T1 link
D3/D4 or ESF framing and SLC-96 compatible
Two frame elastic buffer with 32µs jitter buffer
Insertion and detection of A, B, C, D bits
Signalling freeze, optional debounce
Selectable B8ZS, jammed bit (ZCS) or no zero
code suppression
Yellow and blue alarm signal capabilities
Bipolar violation count, F
T
error count, CRC
error count
Frame and superframe sync. signals, Tx and Rx
Per channel, overall, and remote loop around
8 kHz synchronization output
Digital phase detector between T1 line and ST-
BUS
ST-BUS compatible
Pin compatible with the MH89760
Inductorless clock recovery
Loss of Signal (LOS) indication
Available in standard, narrow and surface
mount formats
MH89760B
MH89760BN
MH89760BS
ISSUE 5
May 1995
Ordering Information
40 Pin DIL Hybrid 1.3" row pitch
40 Pin DIL Hybrid 0.8" row pitch
40 Pin Surface Mount Hybrid
0°C to 70°C
Description
The MH89760B is a complete T1 interface solution,
meeting the Extended Super Frame (ESF), D3/D4
and SLC-96 formats. The MH89760B interfaces to
the DS11.544 Mbit/sec digital trunk.
The MH89760B is a pin-compatible enhancement of
the MH89760, permitting the removal of the tuneable
inductor and inclusion of the external NAND gate
used for generating RxD.
Applications
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DS1/ESF digital trunk interfaces
Computer to PBX interfaces (DMI and CPI)
High speed computer to computer data links
TxSF
C2i
F0i
RxSF
DSTo
DSTi
CSTi0
CSTi1
CSTo
C1.5i
ST-BUS
Timing
Circuitry
1544-2048
Two Frame
Elastic
Buffer
DS1
LINK
INTERFACE
2048 - 1544
Converter
Serial
Control
Interface
Transmitter
RxFDLClk
RxFDL
TxFDLClk
TxFDL
OUTA
OUTB
RxA
RxT
LOS
RxR
RxB
Data
Interface
Receiver
ABCD
Signalling RAM
VDD
XCtl
XSt
Control
Logic
Phase
Detector
Clock
Extractor
DS1
Counter
E1.5o
E8Ko
VSS
Figure 1 - Functional Block Diagram
4-55
MITEL [ MITEL NETWORKS CORPORATION ]
