Preliminary Information
Bit
7-4
3
2
1
0
MH89760B
.
Name
Unused
A
B
C
D
Unused Bits. Will be output as 0’s.
Description
These are the 4 signalling bits as extracted from the received DS1 bit stream.
The bits are debounced for 6 to 9 ms if the debounce feature is enabled via bit 7 in Master
Control Word 1.
Table 11. Per Channel Status Word Output on CSTo
Alarm Detection
The device detects the yellow alarm for both D3/D4
frame format and ESF format. The D3/D4 yellow
alarm will be activated if a ‘0‘ is received in bit
position 2 of every DS0 channel for 600 msec. It will
be released in 200 msec after the contents of the bit
change. The alarm is detectable in the presence of
errors on the line.
The ESF yellow alarm will
become active when the device has detected a string
of eight 0’s followed by eight 1’s in the facility data
link. It is not detectable in the presence of errors on
the line. This means that the ESF yellow alarm will
drop out for relatively short periods of time, so the
system will have to integrate the ESF yellow alarm.
The blue alarm signal, in Master Status Word 2, will
also drop out if there are errors on the line.
Mimic Detection
The mimic bit in Master Status Word 1 will be set if,
during synchronization, a frame alignment pattern
(F
T
or FPS bit pattern) was observed in more than
one position, i.e., if more than one candidate for the
frame synchronization position was observed. It will
be reset when the device resynchronizes. The mimic
bit, the terminal framing error bit and the CRC error
counter can be used separately or together to decide
if the receiver should be forced to reframe.
Bipolar Violation Counter
The Bipolar Violation bit in Master Status Word 1 will
toggle after 256 violations have been detected in the
received signal. It has a maximum refresh time of 96
ms. This means that the bit can not change state
faster than once every 96 ms. For example, if there
are 256 violations in 80 ms the BPV bit will not
change state until 96 ms. Any more errors in that
extra 16 ms are not counted. If there are 256 errors
in 200 ms then the BPV bit will change state after
200 ms. In practical terms this puts an upper limit
on the error rate that can be calculated from the BPV
information, but this rate (1.7 X 10
-3
) is well above
any normal operating condition.
Bits 4 and 3 also provide bipolar violations infor-
mation. Bit 4 will change state after 128 violations.
Bit 3 changes state after 64 bipolar violations. These
bits are refreshed independently and are not subject
to the 96 ms refresh rate described above.
DS1/ST-BUS Phase Difference
An indication of the phase difference between the
ST-BUS and the DS1 frame can be ascertained from
the information provided by the eight bit Phase
Status Word and the Frame Count bit. Channel three
on CSTo contains the Phase Status Word. Bits 7-3 in
this word indicate the number of ST-BUS channels
between the ST-BUS frame pulse and the rising
edge of the E8Ko signal. The remaining three bits
provide one bit resolution within the channel count
indicated by bits 7-3. The frame count bit in Master
Status Word 2 is the ninth and most significant bit of
the phase status word. It will toggle when the phase
status word increments above channel 31, bit 7 or
decrements below channel 0, bit 0. The E8Ko signal
has a specific relationship with received DS1 frame.
The rising edge of E8Ko occurs during bit 2, channel
17 of the received DS1 frame. The Phase Status
Word in conjunction with the frame count bit, can be
used to monitor the phase relationship between the
received DS1 frame and the local ST-BUS frame.
The local 2.048 MHz ST-BUS clock must be phase-
locked to the 1.544 MHz clock extracted from the
received data. When the two clocks are not phase-
locked, the input data rate on the DS1 side will differ
from the output data rate on the ST-BUS side. If the
average input data rate is higher than the average
output data rate, the channel count and bit count in
the phase status word will be seen to decrease over
time, indicating that the E8Ko rising edge, and
therefore the DS1 frame boundary is moving with
respect to the ST-BUS frame pulse. Conversely, a
lower average input data rate will result in an
increase in the phase reading.
In an application where it is necessary to minimize
jitter transfer from the received clock to the local
system clock, a phase lock loop with a relatively
large time constant can be implemented using
information provided by the phase status word. In
such a system, the local 2.048 MHz clock is derived
from a precision VCO. Frequency corrections are
made on the basis of the average trend observed in
4-65
MITEL [ MITEL NETWORKS CORPORATION ]
