Preliminary Information
MT8843
t
t
CDD
DCD
t
t
t
DH, DL
R
t
F
V
V
V
HM
CT
LM
DATA
DCLK
V
V
V
HM
CT
LM
t
t
CH
CL
t
t
R
F
Figure 10 - DATA and DCLK Mode 0 Output Timing*
* VHM=0.7*VDD, VLM=0.3*VDD, VCT=0.5*VDD
t
t
RR
RF
V
V
V
HM
CT
LM
DR
t
RL
Figure 11 - DR Output Timing*
* VHM=0.7*VDD, VLM=0.3*VDD, VCT=0.5*VDD
start
stop
start
stop
start
stop
A/B WIRES
DATA
b7
b6
b6
b0 b1 b2
1
0
b0 b1 b2 b3 b4 b5
b7
b6
b0 b1 b2 b3 b4 b5
b7
b6
1
0
1
0
t
IDD
start
start
start
b0 b1 b2
b7
b0 b1 b2 b3 b4 b5
b7
b0 b1 b2 b3 b4 b5
b7
stop
stop
stop
1/fDCLK0
DCLK
DR
tRL
t
CRD
Figure 12 - Serial Data Interface Timing (MODE 0)
5-35