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MT8880C 参数 Datasheet PDF下载

MT8880C图片预览
型号: MT8880C
PDF下载: 下载PDF文件 查看货源
内容描述: ISO2 -CMOS集成DTMFTransceiver [ISO2-CMOS Integrated DTMFTransceiver]
分类和应用:
文件页数/大小: 18 页 / 315 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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®
ISO
2
-CMOS
MT8880C/MT8880C-1
Integrated DTMF Transceiver
Features
Complete DTMF transmitter/receiver
Central office quality
Low power consumption
Microprocessor port
Adjustable guard time
Automatic tone burst mode
Call progress mode
ISSUE 2
May 1995
Ordering Information
MT8880CE/CE-1
20 Pin Plastic DIP
MT8880CC/CC-1
20 Pin Ceramic DIP
MT8880CS/CS-1
20 Pin SOIC
MT8880CN/CN-1
24 Pin SSOP
MT8880CP/CP-1
28 Pin Plastic LCC
-40°C to +85°C
based upon the industry standard MT8870
monolithic DTMF receiver; the transmitter utilizes a
switched capacitor D/A converter for low distortion,
high accuracy DTMF signalling. Internal counters
provide a burst mode such that tone bursts can be
transmitted with precise timing. A call progress filter
can be selected allowing a microprocessor to
analyze
call
progress
tones.
A
standard
microprocessor bus is provided and is directly
compatible with 6800 series microprocessors. The
MT8880C-1 is functionally identical to the MT8880C
except for the performance of the receiver section,
which is enhanced to accept and reject lower signal
levels.
Applications
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
Description
The MT8880C/C-1 is a monolithic DTMF transceiver
with call progress filter. It is fabricated in Mitel’s
ISO
2
-CMOS technology, which provides low power
dissipation and high reliability. The DTMF receiver is
TONE
D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Status
Register
Data
Bus
Buffer
D0
D1
D2
D3
Tone Burst
Gating Cct.
IN+
IN-
GS
OSC1
OSC2
Oscillator
Circuit
Bias
Circuit
V
DD
V
Ref
V
SS
+
-
Dial
Tone
Filter
Control
Logic
Interrupt
Logic
IRQ/CP
High Group
Filter
Low Group
Filter
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Register
A
Control
Register
B
I/O
Control
Φ2
CS
R/W
RS0
Steering
Logic
Receive Data
Register
ESt
St/GT
Figure 1 - Functional Block Diagram
4-33