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MT8888CE-1 参数 Datasheet PDF下载

MT8888CE-1图片预览
型号: MT8888CE-1
PDF下载: 下载PDF文件 查看货源
内容描述: 综合DTMFTransceiver与英特尔微型接口 [Integrated DTMFTransceiver with Intel Micro Interface]
分类和应用: 电信集成电路光电二极管
文件页数/大小: 16 页 / 305 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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®
MT8888C/MT8888C-1
Integrated DTMF Transceiver
with Intel Micro Interface
Features
Central office quality DTMF transmitter/receiver
Low power consumption
High speed Intel micro interface
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30dBm
ISSUE 2
May 1995
Ordering
MT8888CE/CE-1
MT8888CC/CC-1
MT8888CS/CS-1
MT8888CN/CN-1
Information
20 Pin Plastic DIP
20 Pin Ceramic DIP
20 Pin SOIC
24 Pin SSOP
-40°C to +85°C
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
transmitter utilizes a switched capacitor D/A
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
The MT8888C utilizes an Intel micro interface, which
allows the device to be connected to a number of
popular microcontrollers with minimal external logic.
The MT8888C-1 is functionally identical to the
MT8888C except the receiver is enhanced to accept
lower level signals, and also has a specified low
signal rejection level.
Applications
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
Description
The MT8888C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS
technology offering low power consumption and high
reliability.
TONE
D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Status
Register
Data
Bus
Buffer
D0
D1
D2
D3
Tone Burst
Gating Cct.
IN+
IN-
GS
OSC1
OSC2
Oscillator
Circuit
Bias
Circuit
V
DD
V
Ref
V
SS
+
-
Dial
Tone
Filter
Control
Logic
Interrupt
Logic
IRQ/CP
High Group
Filter
Low Group
Filter
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Register
A
Control
Register
B
I/O
Control
RD
CS
R/W
RS0
Steering
Logic
Receive Data
Register
ESt
St/GT
Figure 1 - Functional Block Diagram
4-91