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MT8889CN 参数 Datasheet PDF下载

MT8889CN图片预览
型号: MT8889CN
PDF下载: 下载PDF文件 查看货源
内容描述: 综合DTMFTransceiver自适应微型接口 [Integrated DTMFTransceiver with Adaptive Micro Interface]
分类和应用: 电信集成电路光电二极管
文件页数/大小: 18 页 / 359 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT8889C/MT8889C-1
The adaptive micro interface provides access to five
internal registers. The read-only Receive Data
Register contains the decoded output of the last
valid DTMF digit received. Data entered into the
write-only Transmit Data Register will determine
which tone pair is to be generated (see Table 1 for
coding details). Transceiver control is accomplished
with two control registers (see Tables 6 and 7), CRA
and CRB, which have the same address. A write
operation to CRB is executed by first setting the
most significant bit (b3) in CRA. The following write
operation to the same address will then be directed
to CRB, and subsequent write cycles will be directed
back to CRA. The read-only status register indicates
the current transceiver state (see Table 8).
A software reset must be included at the beginning
of all programs to initialize the control registers upon
power-up or power reset (see Figure 15). Refer to
Tables 4-7 for bit descriptions of the two control
registers.
The multiplexed IRQ/CP pin can be programmed to
generate an interrupt upon validation of DTMF
signals or when the transmitter is ready for more
data (burst mode only). Alternatively, this pin can be
configured to provide a square-wave output of the
call progress signal. The IRQ/CP pin is an open drain
output and requires an external pull-up resistor (see
Figure 13).
Motorola
RS0
R/W
Intel
WR
RD
FUNCTION
Write to Transmit
Data Register
Read from Receive
Data Register
Write to Control Register
Read from Status Register
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
Table 3. Internal Register Functions
b3
RSEL
b2
IRQ
b1
CP/DTMF
b0
TOUT
Table 4. CRA Bit Positions
b3
C/R
b2
S/D
b1
TEST
b0
BURST
ENABLE
Table 5. CRB Bit Positions
MC6800/6802
A0-A15
MT8889/MT8889C-1
CS
RS0
MC68HC11
A8-A15
AS
AD0-AD3
DS
RW
MT8889C/MT8889C-1
CS
D0-D3
RS0
DS/RD
R/W/WR
VMA
D0-D3
RW
Φ2
(a)
D0-D3
R/W/WR
DS/RD
MC6809
MT8889/MT8889C-1
8031/8051
8080/8085
MT8889C/MT8889C-1
A0-A15
CS
RS0
A8-A15
CS
D0-D3
RS0
DS/RD
R/W/WR
(b)
Q
E
D0-D3
R/W
ALE
D0-D3
R/W/WR
DS/RD
P0
RD
WR
Figure 12 a) & b) - MT8889 Interface Connections for Various Intel and Motorola Micros
4-115