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MT88L89AP 参数 Datasheet PDF下载

MT88L89AP图片预览
型号: MT88L89AP
PDF下载: 下载PDF文件 查看货源
内容描述: 3V集成DTMFTransceiver自适应微型接口 [3V Integrated DTMFTransceiver with Adaptive Micro Interface]
分类和应用:
文件页数/大小: 20 页 / 355 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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®
MT88L89
3V Integrated DTMF Transceiver
Advance Information
with Adaptive Micro Interface
Features
Central office quality DTMF transmitter/
receiver
Low voltage operation (2.7-3.6V)
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30dBm
Adaptive micro interface enables compatibility
with existing MT8880/MT8888 designs
DTMF transmitter/receiver power down via
register control
ISSUE 1
May 1995
Ordering Information
MT88L89AE
20 Pin Plastic DIP
MT88L89AC
20 Pin Ceramic DIP
MT88L89AS
20 Pin SOIC
MT88L89AN
24 Pin SSOP
MT88L89AP
28 Pin PLCC
-40°C to +85°C
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
transmitter utilizes a switched capacitor D/A
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
The MT88L89 utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic. The MT88L89 provides enhanced power down
features.
The transmitter and receiver may
independently be powered down via register control.
Applications
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
Description
The MT88L89 is a monolithic DTMF transceiver with
call progress filter.
It is fabricated in CMOS
technology offering low power consumption and high
reliability.
TONE
D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Status
Register
Data
Bus
Buffer
D0
D1
D2
D3
Tone Burst
Gating Cct.
IN+
IN-
GS
OSC1
OSC2
Oscillator
Circuit
Bias
Circuit
V
DD
V
Ref
V
SS
+
-
Dial
Tone
Filter
Control
Logic
Interrupt
Logic
IRQ/CP
High Group
Filter
Low Group
Filter
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Register
A
Control
Register
B
I/O
Control
DS/RD
CS
R/W/WR
RS0
Steering
Logic
Receive Data
Register
ESt
St/GT
Figure 1 - Functional Block Diagram
4-125