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MT8941AP 参数 Datasheet PDF下载

MT8941AP图片预览
型号: MT8941AP
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS ST- BUS⑩家庭高级T1 / CEPT数字中继锁相环 [CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL]
分类和应用:
文件页数/大小: 18 页 / 249 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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CMOS MT8941  
oscillators of DPLL #1 and DPLL #2 to have  
maximum tolerances of ±32ppm and ±50ppm  
respectively.  
it is recommended to use a ±32 ppm oscillator for  
DPLL #2 and a ±100 ppm oscillator for DPLL #1.  
Differences between MT8941 and MT8940  
However, if DPLL #1 and DPLL #2 are daisy-chained  
as shown in Figures 9 and 10, the output clock  
tolerance of DPLL #1 will be equal to that of the  
DPLL #2 oscillator when DPLL #2 is free-running. In  
this case, the oscillator tolerance of DPLL #1 has no  
impact on its output clock tolerance. For this reason,  
The MT8941 and MT8940 are pin and mode  
compatible for most applications. However, the user  
should take note of the following differences between  
the two parts.  
a) Distributed Timing  
Data Bus  
Line Card 1  
8 kHz Reference Signal  
MT8940  
Clocks  
M
U
X
Line Card n  
8 kHz Reference Signal  
MT8940  
Clocks  
b) Centralized Timing  
Data Bus  
Line Card 1  
8 kHz Reference Signal  
M
U
MT8941  
X
Clocks  
Line Card n  
8 kHz Reference Signal  
Figure 8 - Application Differences between the MT8940 and MT8941  
3-51