®
ISO-CMOS ST-BUS™ FAMILY
MT8952B
HDLC Protocol Controller
Features
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Formats data as per X.25 (CCITT) level-2
standards
Go-Ahead sequence generation and detection
Single byte address recognition
Microprocessor port and directly accessible
registers for flexible operation and control
19 byte FIFO in both send and receive paths
Handshake signals for multiplexing data links
High speed serially clocked output (2.5 Mbps)
ST-BUS compatibility with programmable
channel selection for data and separate
timeslot for control information
Independent watchdog timer
Facility to disable protocol functions
Low power ISO-CMOS technology
Data link controllers and protocol generators
Digital sets, PBXs and private packet networks
D-channel controller for ISDN basic access
C-channel controller to Digital Network
Interface Circuits (typically MT8972)
Interprocessor communication
ISSUE 5
May 1995
Ordering Information
MT8952BC
28 Pin Ceramic DIP
MT8952BE
28 Pin Plastic DIP
MT8952BP
28 Pin PLCC
MT8952BS
28 Pin SOIC
-40°C to 85°C
Description
The MT8952B HDLC Protocol Controller frames and
formats data packets according to X.25 (Level 2)
Recommendations from the CCITT.
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Applications
TEOP
C-Channel
Interface
Transmit
FIFO
Transmit
Logic
Zero
Insertion
Flag/Abort
Generator
CDSTo
D0-D7
Micro
Processor
R/W
CS
E
IRQ
WD
Interface
Control
Address
Decoder
Interrupt
Registers
and Status
Register
Timing
Logic
F0i
CKi
RxCEN
TxCEN
A0-A3
V
DD
V
SS
RST
Receive
FIFO
Receive Logic
Address
Detection
Zero
Deletion
Flag/Abort/
Idle
Detection
CDSTi
REOP
Figure 1 - Functional Block Diagram
3-61
MITEL [ MITEL NETWORKS CORPORATION ]
