ISO
2
-CMOS
Powerdown
Powerdown of the chip is achieved in several ways:
Internal Control:
1)
Initial Power-up. Initial application of V
DD
and
V
EE
causes powerdown for a period of 25 clock
cycles and during this period the chip will
accept input only from C2i. The B-register is
reset to zero forcing SD0-5 to be inactive. Bits
0-5 of Register A (gain adjust bits) are forced
to zero and bits 6 and 7 of Register A become
logic high thus reinforcing the powerdown.
Loss of C2i. Powerdown is entered 10 to 40
µs after C2i has assumed a continuous logic
high (V
DD
). In this condition the chip will be in
the same state as in (1) above.
Note:
If C2i stops at a continuous logic low
(GNDD), the digital data and status is
indeterminate.
MT8960/61/62/63/64/65/66/67
External Control:
1)
Register A. Powerdown is controlled by bits 6
and 7 ( when both at logic high) of Register A
which in turn receives its control word input
via CSTi, when F1i is low and CA input is
either at V
EE
or GNDD. Power is removed
from the filters and analog sections of the chip.
The analog ouput buffer at V
R
will be
connected to GNDA. DSTo becomes high
impedance and the clocks to the majority of the
logic are stopped. SD outputs are unaffected
and may be updated as normal.
CSTi Input. With CA at V
EE
and CSTi held at
continuous logic high the chip assumes the
same state as described in External Control
(1) above.
2)
2)
Message
Waiting
MT8960/61/64/65
From ST-BUS
From ST-BUS
Master Clock
to ST-BUS
5V
Alignment
Register Select
CSTi
DSTi
C2i
DSTo
V
DD
F1i
CA
SD3
SD2
GNDD
V
Ref
GNDA
V
R
ANUL
V
X
V
EE
SD0
SD1
-5V
0.1µF
Ring Trip
Filter
(With Relay
Drive)
Gain
Section
2/4 Wire
Converter
2.5V
(With Relay
Drive)
-100V DC
Telephone
Line
Ring Feed
(With Relay
Drive)
-48V DC
-48V DC
90V
RMS
Figure 7 - Typical Use of the Special Drive Outputs
6-27
MITEL [ MITEL NETWORKS CORPORATION ]
