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MT8972BC 参数 Datasheet PDF下载

MT8972BC图片预览
型号: MT8972BC
PDF下载: 下载PDF文件 查看货源
内容描述: ISO2 -CMOS ST- BUS⑩家庭数字用户接口电路数字网络接口电路 [ISO2-CMOS ST-BUS⑩ FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit]
分类和应用: 网络接口
文件页数/大小: 20 页 / 393 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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®
ISO
2
-CMOS ST-BUS™ FAMILY
MT8971B/72B
Digital Subscriber Interface Circuit
Digital Network Interface Circuit
Features
Full duplex transmission over a single twisted
pair
Selectable 80 or 160 kbit/s line rate
Adaptive echo cancellation
Up to 3km (8971B) and 4 km (8972B)
ISDN compatible (2B+D) data format
Transparent modem capability
Frame synchronization and clock extraction
MITEL ST-BUS compatible
Low power (typically 50 mW), single 5V supply
ISSUE 7
May 1995
Ordering Information
MT8971BE
22 Pin Plastic DIP
MT8972BE
22 Pin Plastic DIP
MT8972BC
22 Pin Ceramic DIP
MT8971BP
28 Pin PLCC
MT8972BP
28 Pin PLCC
-40°C to
+
85°C
Description
The MT8971B (DSIC) and MT8972B (DNIC) are
multi-function devices capable of providing high
speed, full duplex digital transmission up to 160
kbit/s over a twisted wire pair. They use adaptive
echo-cancelling techniques and transfer data in
(2B+D) format compatible to the ISDN basic rate.
Several modes of operation allow an easy interface
to digital telecommunication networks including use
as a high speed limited distance modem with data
rates up to 160 kbit/s.
Both devices function
identically but with the DSIC having a shorter
maximum loop reach specification. The generic
"DNIC" will be used to reference both devices unless
otherwise noted.
The MT8971B/72B is fabricated in Mitel’s ISO
2
-
CMOS process.
Applications
Digital subscriber lines
High speed data transmission over twisted
wires
Digital PABX line cards and telephone sets
80 or 160 kbit/s single chip modem
DSTi/Di
CDSTi/
CDi
Transmit
Interface
Prescrambler
Scrambler
Differentially
Encoded Biphase
Transmitter
Transmit
Filter &
Line Driver
L
OUT
F0/CLD
C4/TCK
F0o/RCK
MS0
MS1
MS2
RegC
Control
Register
Transmit
Timing
V
Bias
Address
Echo Canceller
Error
Signal
Echo Estimate
DPLL
MUX
L
OUT
DIS
Master Clock
Phase Locked
Transmit/
Clock
Receive
Timing &
Control
Sync Detect
Status
Receive
Precan
+
Receive
Filter
-1
+2
L
IN
OSC2
DSTo/Do
CDSTo/
CDo
Receive
Interface
De-
Prescrambler
Descrambler
Differentially
Encoded Biphase
Receiver
OSC1
V
DD
V
SS
V
Bias
V
Ref
Figure 1 - Functional Block Diagram
9-107